UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:0 h, 49 min, 16 s
Processing Date:Fri Jun 20 17:59:43 2025 (UTC)
Requested start:1433251327 → Fri Jun 6 13:21:49 2025 (UTC)
Requested stop:1433662380 → Wed Jun 11 07:32:42 2025 (UTC)
Requested livetime:411053 sec → 4.758 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (533): V1:SDB1_OMC1_in2_0 [click here to expand/hide] [link to here]


V1 (533): V1:SDB1_OMC1_err_0 [click here to expand/hide] [link to here]


V2 (468): V1:SDB1_OMC_L_Peltier_cur_0 [click here to expand/hide] [link to here]


V3 (343): V1:SDB1_OMC1_PZT_out_0 [click here to expand/hide] [link to here]


V4 (343): V1:SDB1_OMC1_PZT_corr_clip_0 [click here to expand/hide] [link to here]


V5 (303): V1:SDB1_OMC1_Peltier_cmd_0 [click here to expand/hide] [link to here]


V6 (261): V1:SDB1_OMC1_Peltier_out_0 [click here to expand/hide] [link to here]


V7 (0): V1:SDB1_spiral_ramp_0 [click here to expand/hide] [link to here]


V8 (0): V1:SDB1_spiral_TY_0 [click here to expand/hide] [link to here]


V9 (0): V1:SDB1_spiral_TX_0 [click here to expand/hide] [link to here]


V10 (0): V1:SDB1_slow_shutter_OMC1_T1_slow_0 [click here to expand/hide] [link to here]


V11 (0): V1:SDB1_slow_shutter_OMC1_T1_fast_0 [click here to expand/hide] [link to here]


V12 (0): V1:SDB1_fast_shutter_sw_0 [click here to expand/hide] [link to here]


V13 (0): V1:SDB1_Quadrants_elapsed_time_0 [click here to expand/hide] [link to here]


V14 (0): V1:SDB1_Quadrants_CfgChange_0 [click here to expand/hide] [link to here]


V15 (0): V1:SDB1_OMC_elapsed_time_0 [click here to expand/hide] [link to here]


V16 (0): V1:SDB1_OMC_R_T0_0 [click here to expand/hide] [link to here]


V17 (0): V1:SDB1_OMC_R_Peltier_cur_0 [click here to expand/hide] [link to here]


V18 (0): V1:SDB1_OMC_L_T0_0 [click here to expand/hide] [link to here]


V19 (0): V1:SDB1_OMC_CfgChange_0 [click here to expand/hide] [link to here]


V20 (0): V1:SDB1_OMC1_T1_0 [click here to expand/hide] [link to here]


V21 (0): V1:SDB1_OMC1_PD_DC_check_0 [click here to expand/hide] [link to here]


V22 (0): V1:SDB1_OMC1_DC_sw_0 [click here to expand/hide] [link to here]


V23 (0): V1:SDB1_OMC1_AC_sw_0 [click here to expand/hide] [link to here]


V24 (0): V1:SDB1_OMC1_AC_check_0 [click here to expand/hide] [link to here]


V25 (0): V1:SDB1_NOISE_gene_0 [click here to expand/hide] [link to here]


V26 (0): V1:SDB1_NOISE_flt_0 [click here to expand/hide] [link to here]


V27 (0): V1:SDB1_NOISE_cmd_0 [click here to expand/hide] [link to here]


V28 (0): V1:SDB1_MAR_TZ_corr_0 [click here to expand/hide] [link to here]


V29 (0): V1:SDB1_MAR_TY_corr_0 [click here to expand/hide] [link to here]


V30 (0): V1:SDB1_MAR_TX_corr_0 [click here to expand/hide] [link to here]


V31 (0): V1:SDB1_MAR_TXYZ_enbl_0 [click here to expand/hide] [link to here]


V32 (0): V1:SDB1_MAR_COIL_disable_inv_0 [click here to expand/hide] [link to here]


V33 (0): V1:SDB1_LSC_ENABLE_0 [click here to expand/hide] [link to here]


V34 (0): V1:SDB1_LC_elapsed_time_0 [click here to expand/hide] [link to here]


V35 (0): V1:SDB1_LC_Z_err_0 [click here to expand/hide] [link to here]


V36 (0): V1:SDB1_LC_Z_corr_0 [click here to expand/hide] [link to here]


V37 (0): V1:SDB1_LC_Z_0 [click here to expand/hide] [link to here]


V38 (0): V1:SDB1_LC_Y_fb_0 [click here to expand/hide] [link to here]


V39 (0): V1:SDB1_LC_Y_enbl_0 [click here to expand/hide] [link to here]


V40 (0): V1:SDB1_LC_Y_corr_0 [click here to expand/hide] [link to here]


V41 (0): V1:SDB1_LC_Y_0 [click here to expand/hide] [link to here]


V42 (0): V1:SDB1_LC_X_corr_0 [click here to expand/hide] [link to here]


V43 (0): V1:SDB1_LC_X_0 [click here to expand/hide] [link to here]


V44 (0): V1:SDB1_LC_TZ_fb_0 [click here to expand/hide] [link to here]


V45 (0): V1:SDB1_LC_TZ_err_0 [click here to expand/hide] [link to here]


V46 (0): V1:SDB1_LC_TZ_corr_0 [click here to expand/hide] [link to here]


V47 (0): V1:SDB1_LC_TZ_0 [click here to expand/hide] [link to here]


V48 (0): V1:SDB1_LC_TY_fb_0 [click here to expand/hide] [link to here]


V49 (0): V1:SDB1_LC_TY_err_pre_0 [click here to expand/hide] [link to here]


V50 (0): V1:SDB1_LC_TY_err_0 [click here to expand/hide] [link to here]


V51 (0): V1:SDB1_LC_TY_corr_0 [click here to expand/hide] [link to here]


V52 (0): V1:SDB1_LC_TY_0 [click here to expand/hide] [link to here]


V53 (0): V1:SDB1_LC_TX_fb_0 [click here to expand/hide] [link to here]


V54 (0): V1:SDB1_LC_TX_err_pre_0 [click here to expand/hide] [link to here]


V55 (0): V1:SDB1_LC_TX_err_0 [click here to expand/hide] [link to here]


V56 (0): V1:SDB1_LC_TX_corr_0 [click here to expand/hide] [link to here]


V57 (0): V1:SDB1_LC_TXY_floating_enbl_0 [click here to expand/hide] [link to here]


V58 (0): V1:SDB1_LC_TXYZ_enbl_0 [click here to expand/hide] [link to here]


V59 (0): V1:SDB1_LC_TX_0 [click here to expand/hide] [link to here]


V60 (0): V1:SDB1_LC_LVDT_FR_V_err_0 [click here to expand/hide] [link to here]


V61 (0): V1:SDB1_LC_LVDT_FR_H_err_0 [click here to expand/hide] [link to here]


V62 (0): V1:SDB1_LC_LVDT_FL_V_err_0 [click here to expand/hide] [link to here]


V63 (0): V1:SDB1_LC_LVDT_FL_H_err_0 [click here to expand/hide] [link to here]


V64 (0): V1:SDB1_LC_LVDT_BR_V_err_0 [click here to expand/hide] [link to here]


V65 (0): V1:SDB1_LC_LVDT_BR_H_err_0 [click here to expand/hide] [link to here]


V66 (0): V1:SDB1_LC_LVDT_BL_V_err_0 [click here to expand/hide] [link to here]


V67 (0): V1:SDB1_LC_LVDT_BL_H_err_0 [click here to expand/hide] [link to here]


V68 (0): V1:SDB1_LC_CfgChange_0 [click here to expand/hide] [link to here]


V69 (0): V1:SDB1_LC_COIL_disable_inv_0 [click here to expand/hide] [link to here]


V70 (0): V1:SDB1_LC_COIL_FR_V_0 [click here to expand/hide] [link to here]


V71 (0): V1:SDB1_LC_COIL_FR_H_0 [click here to expand/hide] [link to here]


V72 (0): V1:SDB1_LC_COIL_FL_V_0 [click here to expand/hide] [link to here]


V73 (0): V1:SDB1_LC_COIL_FL_H_0 [click here to expand/hide] [link to here]


V74 (0): V1:SDB1_LC_COIL_BR_V_0 [click here to expand/hide] [link to here]


V75 (0): V1:SDB1_LC_COIL_BR_H_0 [click here to expand/hide] [link to here]


V76 (0): V1:SDB1_LC_COIL_BL_V_0 [click here to expand/hide] [link to here]


V77 (0): V1:SDB1_LC_COIL_BL_H_0 [click here to expand/hide] [link to here]


V78 (0): V1:SDB1_LC_B5_QD2_enbl_safe_0 [click here to expand/hide] [link to here]


V79 (0): V1:SDB1_LC_B5_QD2_enbl_0 [click here to expand/hide] [link to here]


V80 (0): V1:SDB1_LC_B1s_QD2_enbl_safe_0 [click here to expand/hide] [link to here]


V81 (0): V1:SDB1_LC_B1_DARM_enbl_0 [click here to expand/hide] [link to here]


V82 (0): V1:SDB1_FI_in_0 [click here to expand/hide] [link to here]


V83 (0): V1:SDB1_FI_elapsed_time_0 [click here to expand/hide] [link to here]


V84 (0): V1:SDB1_FI_CfgChange_0 [click here to expand/hide] [link to here]


V85 (0): V1:SDB1_FAST_SHUTTER_elapsed_time_0 [click here to expand/hide] [link to here]


V86 (0): V1:SDB1_FAST_SHUTTER_CfgChange_0 [click here to expand/hide] [link to here]


V87 (0): V1:SDB1_B5_QD2_sum_0 [click here to expand/hide] [link to here]


V88 (0): V1:SDB1_B5_QD2_safe_0 [click here to expand/hide] [link to here]


V89 (0): V1:SDB1_B5_QD2_V_pre_0 [click here to expand/hide] [link to here]


V90 (0): V1:SDB1_B5_QD2_V_offset_0 [click here to expand/hide] [link to here]


V91 (0): V1:SDB1_B5_QD2_V_0 [click here to expand/hide] [link to here]


V92 (0): V1:SDB1_B5_QD2_TY_err_0 [click here to expand/hide] [link to here]


V93 (0): V1:SDB1_B5_QD2_TX_err_0 [click here to expand/hide] [link to here]


V94 (0): V1:SDB1_B5_QD2_H_pre_0 [click here to expand/hide] [link to here]


V95 (0): V1:SDB1_B5_QD2_H_offset_0 [click here to expand/hide] [link to here]


V96 (0): V1:SDB1_B5_QD2_H_0 [click here to expand/hide] [link to here]


V97 (0): V1:SDB1_B5_QD1_sum_0 [click here to expand/hide] [link to here]


V98 (0): V1:SDB1_B5_QD1_V_0 [click here to expand/hide] [link to here]


V99 (0): V1:SDB1_B5_QD1_H_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr