OUTPUT DIRECTORY ./report OUTPUT VERBOSITY 1 TARGET OMICRON V1:Hrec_hoft_16384Hz TARGET CLUSTERDT 0.1 TARGET SNRMIN 7 COINC TIMEWIN 1.0 VETO UPMIN 0.4 VETO UMIN 10 VETO PRINT 0 VETO PERF 5 8 10 20 VETO PERFPRINT 1 0 SOURCE CLUSTERDT 0.1 SOURCE OMICRON V1:SDB1_B5_QD1_H SOURCE OMICRON V1:SDB1_B5_QD1_V SOURCE OMICRON V1:SDB1_B5_QD1_sum SOURCE OMICRON V1:SDB1_B5_QD2_H SOURCE OMICRON V1:SDB1_B5_QD2_H_offset SOURCE OMICRON V1:SDB1_B5_QD2_H_pre SOURCE OMICRON V1:SDB1_B5_QD2_TX_err SOURCE OMICRON V1:SDB1_B5_QD2_TY_err SOURCE OMICRON V1:SDB1_B5_QD2_V SOURCE OMICRON V1:SDB1_B5_QD2_V_offset SOURCE OMICRON V1:SDB1_B5_QD2_V_pre SOURCE OMICRON V1:SDB1_B5_QD2_safe SOURCE OMICRON V1:SDB1_B5_QD2_sum SOURCE OMICRON V1:SDB1_FAST_SHUTTER_CfgChange SOURCE OMICRON V1:SDB1_FAST_SHUTTER_elapsed_time SOURCE OMICRON V1:SDB1_FI_CfgChange SOURCE OMICRON V1:SDB1_FI_elapsed_time SOURCE OMICRON V1:SDB1_FI_in SOURCE OMICRON V1:SDB1_LC_B1_DARM_enbl SOURCE OMICRON V1:SDB1_LC_B1s_QD2_enbl_safe SOURCE OMICRON V1:SDB1_LC_B5_QD2_enbl SOURCE OMICRON V1:SDB1_LC_B5_QD2_enbl_safe SOURCE OMICRON V1:SDB1_LC_COIL_BL_H SOURCE OMICRON V1:SDB1_LC_COIL_BL_V SOURCE OMICRON V1:SDB1_LC_COIL_BR_H SOURCE OMICRON V1:SDB1_LC_COIL_BR_V SOURCE OMICRON V1:SDB1_LC_COIL_FL_H SOURCE OMICRON V1:SDB1_LC_COIL_FL_V SOURCE OMICRON V1:SDB1_LC_COIL_FR_H SOURCE OMICRON V1:SDB1_LC_COIL_FR_V SOURCE OMICRON V1:SDB1_LC_COIL_disable_inv SOURCE OMICRON V1:SDB1_LC_CfgChange SOURCE OMICRON V1:SDB1_LC_LVDT_BL_H_err SOURCE OMICRON V1:SDB1_LC_LVDT_BL_V_err SOURCE OMICRON V1:SDB1_LC_LVDT_BR_H_err SOURCE OMICRON V1:SDB1_LC_LVDT_BR_V_err SOURCE OMICRON V1:SDB1_LC_LVDT_FL_H_err SOURCE OMICRON V1:SDB1_LC_LVDT_FL_V_err SOURCE OMICRON V1:SDB1_LC_LVDT_FR_H_err SOURCE OMICRON V1:SDB1_LC_LVDT_FR_V_err SOURCE OMICRON V1:SDB1_LC_TX SOURCE OMICRON V1:SDB1_LC_TXYZ_enbl SOURCE OMICRON V1:SDB1_LC_TXY_floating_enbl SOURCE OMICRON V1:SDB1_LC_TX_corr SOURCE OMICRON V1:SDB1_LC_TX_err SOURCE OMICRON V1:SDB1_LC_TX_err_pre SOURCE OMICRON V1:SDB1_LC_TX_fb SOURCE OMICRON V1:SDB1_LC_TY SOURCE OMICRON V1:SDB1_LC_TY_corr SOURCE OMICRON V1:SDB1_LC_TY_err SOURCE OMICRON V1:SDB1_LC_TY_err_pre SOURCE OMICRON V1:SDB1_LC_TY_fb SOURCE OMICRON V1:SDB1_LC_TZ SOURCE OMICRON V1:SDB1_LC_TZ_corr SOURCE OMICRON V1:SDB1_LC_TZ_err SOURCE OMICRON V1:SDB1_LC_TZ_fb SOURCE OMICRON V1:SDB1_LC_X SOURCE OMICRON V1:SDB1_LC_X_corr SOURCE OMICRON V1:SDB1_LC_Y SOURCE OMICRON V1:SDB1_LC_Y_corr SOURCE OMICRON V1:SDB1_LC_Y_enbl SOURCE OMICRON V1:SDB1_LC_Y_fb SOURCE OMICRON V1:SDB1_LC_Z SOURCE OMICRON V1:SDB1_LC_Z_corr SOURCE OMICRON V1:SDB1_LC_Z_err SOURCE OMICRON V1:SDB1_LC_elapsed_time SOURCE OMICRON V1:SDB1_LSC_ENABLE SOURCE OMICRON V1:SDB1_MAR_COIL_disable_inv SOURCE OMICRON V1:SDB1_MAR_TXYZ_enbl SOURCE OMICRON V1:SDB1_MAR_TX_corr SOURCE OMICRON V1:SDB1_MAR_TY_corr SOURCE OMICRON V1:SDB1_MAR_TZ_corr SOURCE OMICRON V1:SDB1_NOISE_cmd SOURCE OMICRON V1:SDB1_NOISE_flt SOURCE OMICRON V1:SDB1_NOISE_gene SOURCE OMICRON V1:SDB1_OMC1_AC_check SOURCE OMICRON V1:SDB1_OMC1_AC_sw SOURCE OMICRON V1:SDB1_OMC1_DC_sw SOURCE OMICRON V1:SDB1_OMC1_PD_DC_check SOURCE OMICRON V1:SDB1_OMC1_PZT_corr_clip SOURCE OMICRON V1:SDB1_OMC1_PZT_out SOURCE OMICRON V1:SDB1_OMC1_Peltier_cmd SOURCE OMICRON V1:SDB1_OMC1_Peltier_out SOURCE OMICRON V1:SDB1_OMC1_T1 SOURCE OMICRON V1:SDB1_OMC1_err SOURCE OMICRON V1:SDB1_OMC1_in2 SOURCE OMICRON V1:SDB1_OMC_CfgChange SOURCE OMICRON V1:SDB1_OMC_L_Peltier_cur SOURCE OMICRON V1:SDB1_OMC_L_T0 SOURCE OMICRON V1:SDB1_OMC_R_Peltier_cur SOURCE OMICRON V1:SDB1_OMC_R_T0 SOURCE OMICRON V1:SDB1_OMC_elapsed_time SOURCE OMICRON V1:SDB1_Quadrants_CfgChange SOURCE OMICRON V1:SDB1_Quadrants_elapsed_time SOURCE OMICRON V1:SDB1_fast_shutter_sw SOURCE OMICRON V1:SDB1_slow_shutter_OMC1_T1_fast SOURCE OMICRON V1:SDB1_slow_shutter_OMC1_T1_slow SOURCE OMICRON V1:SDB1_spiral_TX SOURCE OMICRON V1:SDB1_spiral_TY SOURCE OMICRON V1:SDB1_spiral_ramp