UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:6 h, 36 min, 55 s
Processing Date:Thu Feb 13 16:25:56 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:825629 sec → 9.556 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (5025): V1:LSC_DARM_ERR_0 [click here to expand/hide] [link to here]


V1 (5021): V1:LSC_DARM_INPUT_0 [click here to expand/hide] [link to here]


V2 (4836): V1:LSC_DCP_DARM_CORR_FLT_LF_0 [click here to expand/hide] [link to here]


V3 (4484): V1:LSC_DARM_CORR_raw_0 [click here to expand/hide] [link to here]


V4 (4409): V1:LSC_DCP_DARM_ERR_FLT_HF_0 [click here to expand/hide] [link to here]


V5 (4367): V1:LSC_DCP_DARM_ERR_FLT_HF_DEL_0 [click here to expand/hide] [link to here]


V6 (3998): V1:LSC_DCP_DARM_ERR_FLT_LF_0 [click here to expand/hide] [link to here]


V7 (3970): V1:LSC_DCP_DARM_ERR_FLT_LF_DEL_0 [click here to expand/hide] [link to here]


V8 (1899): V1:LSC_DCP_MM_RE_0 [click here to expand/hide] [link to here]


V9 (1443): V1:LSC_DCP_MM_IM_0 [click here to expand/hide] [link to here]


V10 (1330): V1:LSC_NE_CORR_0 [click here to expand/hide] [link to here]


V11 (1322): V1:LSC_NI_CORR_0 [click here to expand/hide] [link to here]


V12 (1264): V1:LSC_DCP_DARM_CORR_FLT_HF_0 [click here to expand/hide] [link to here]


V13 (1258): V1:LSC_DCP_NORM_0 [click here to expand/hide] [link to here]


V14 (212): V1:LSC_PR_CORR_0 [click here to expand/hide] [link to here]


V15 (209): V1:LSC_PRCL_INPUT_0 [click here to expand/hide] [link to here]


V16 (209): V1:LSC_PRCL_ERR_0 [click here to expand/hide] [link to here]


V17 (209): V1:LSC_PRCL_0 [click here to expand/hide] [link to here]


V18 (200): V1:LSC_PRCL_DARM_flt_0 [click here to expand/hide] [link to here]


V19 (188): V1:LSC_PRCL_CORR_raw_0 [click here to expand/hide] [link to here]


V20 (188): V1:LSC_PRCL_CORR_0 [click here to expand/hide] [link to here]


V21 (104): V1:LSC_MICH_INPUT_0 [click here to expand/hide] [link to here]


V22 (104): V1:LSC_MICH_ERR_0 [click here to expand/hide] [link to here]


V23 (104): V1:LSC_MICH_0 [click here to expand/hide] [link to here]


V24 (101): V1:LSC_MICH_SET_IN_0 [click here to expand/hide] [link to here]


V25 (101): V1:LSC_MICH_SET_CORR_0 [click here to expand/hide] [link to here]


V26 (79): V1:LSC_MICH_DARM_flt_0 [click here to expand/hide] [link to here]


V27 (79): V1:LSC_MICH_DARM_CORR_0 [click here to expand/hide] [link to here]


V28 (79): V1:LSC_MICH_CORR_0 [click here to expand/hide] [link to here]


V29 (78): V1:LSC_MICH_SET_INPUT_0 [click here to expand/hide] [link to here]


V30 (70): V1:LSC_SRCL_CORR_0 [click here to expand/hide] [link to here]


V31 (47): V1:LSC_SRCL_INPUT_0 [click here to expand/hide] [link to here]


V32 (47): V1:LSC_SRCL_ERR_0 [click here to expand/hide] [link to here]


V33 (47): V1:LSC_SRCL_0 [click here to expand/hide] [link to here]


V34 (12): V1:LSC_SRCL_DARM_flt_0 [click here to expand/hide] [link to here]


V35 (0): V1:LSC_SRCL_SET_EN_TRIG_0 [click here to expand/hide] [link to here]


V36 (0): V1:LSC_SRCL_SET_ENBL_0 [click here to expand/hide] [link to here]


V37 (0): V1:LSC_SRCL_SET_CORR_FLT_0 [click here to expand/hide] [link to here]


V38 (0): V1:LSC_SRCL_SET_CORR_CLIP_0 [click here to expand/hide] [link to here]


V39 (0): V1:LSC_SRCL_NOISE_0 [click here to expand/hide] [link to here]


V40 (0): V1:LSC_SRCL_DARM_CORR_0 [click here to expand/hide] [link to here]


V41 (0): V1:LSC_PR_LOCK_FLAG_0 [click here to expand/hide] [link to here]


V42 (0): V1:LSC_PRCL_TRIGGER_INPUT_0 [click here to expand/hide] [link to here]


V43 (0): V1:LSC_PRCL_TRIGGER_IN_0 [click here to expand/hide] [link to here]


V44 (0): V1:LSC_PRCL_TRIG_0 [click here to expand/hide] [link to here]


V45 (0): V1:LSC_PRCL_NOISE_0 [click here to expand/hide] [link to here]


V46 (0): V1:LSC_PRCL_DARM_CORR_0 [click here to expand/hide] [link to here]


V47 (0): V1:LSC_NOISE_0 [click here to expand/hide] [link to here]


V48 (0): V1:LSC_NI_VIOLIN_CORR_0 [click here to expand/hide] [link to here]


V49 (0): V1:LSC_NI_VIOLIN8_ERR_0 [click here to expand/hide] [link to here]


V50 (0): V1:LSC_NI_VIOLIN7_ERR_0 [click here to expand/hide] [link to here]


V51 (0): V1:LSC_NI_VIOLIN6_ERR_0 [click here to expand/hide] [link to here]


V52 (0): V1:LSC_NI_VIOLIN5_ERR_0 [click here to expand/hide] [link to here]


V53 (0): V1:LSC_NI_VIOLIN4_ERR_0 [click here to expand/hide] [link to here]


V54 (0): V1:LSC_NI_VIOLIN3_ERR_0 [click here to expand/hide] [link to here]


V55 (0): V1:LSC_NI_VIOLIN2_ERR_0 [click here to expand/hide] [link to here]


V56 (0): V1:LSC_NI_VIOLIN1_ERR_0 [click here to expand/hide] [link to here]


V57 (0): V1:LSC_NI_LOCK_FLAG_0 [click here to expand/hide] [link to here]


V58 (0): V1:LSC_NI_HB_moni_0 [click here to expand/hide] [link to here]


V59 (0): V1:LSC_NE_VIOLIN_CORR_0 [click here to expand/hide] [link to here]


V60 (0): V1:LSC_NE_VIOLIN8_ERR_0 [click here to expand/hide] [link to here]


V61 (0): V1:LSC_NE_VIOLIN7_ERR_0 [click here to expand/hide] [link to here]


V62 (0): V1:LSC_NE_VIOLIN6_ERR_0 [click here to expand/hide] [link to here]


V63 (0): V1:LSC_NE_VIOLIN5_ERR_0 [click here to expand/hide] [link to here]


V64 (0): V1:LSC_NE_VIOLIN4_ERR_0 [click here to expand/hide] [link to here]


V65 (0): V1:LSC_NE_VIOLIN3_ERR_0 [click here to expand/hide] [link to here]


V66 (0): V1:LSC_NE_VIOLIN2_ERR_0 [click here to expand/hide] [link to here]


V67 (0): V1:LSC_NE_VIOLIN1_ERR_0 [click here to expand/hide] [link to here]


V68 (0): V1:LSC_NE_LOCK_FLAG_0 [click here to expand/hide] [link to here]


V69 (0): V1:LSC_NArm_TRIG_0 [click here to expand/hide] [link to here]


V70 (0): V1:LSC_NArm_NOISE_0 [click here to expand/hide] [link to here]


V71 (0): V1:LSC_NArm_LOCK_ON_0 [click here to expand/hide] [link to here]


V72 (0): V1:LSC_NArm_INPUT_0 [click here to expand/hide] [link to here]


V73 (0): V1:LSC_NArm_ERR_0 [click here to expand/hide] [link to here]


V74 (0): V1:LSC_NArm_CORR_0 [click here to expand/hide] [link to here]


V75 (0): V1:LSC_NArm_0 [click here to expand/hide] [link to here]


V76 (0): V1:LSC_MICH_TRIGGER_INPUT_0 [click here to expand/hide] [link to here]


V77 (0): V1:LSC_MICH_TRIGGER_0 [click here to expand/hide] [link to here]


V78 (0): V1:LSC_MICH_TRIG_0 [click here to expand/hide] [link to here]


V79 (0): V1:LSC_MICH_SET_TRIG_0 [click here to expand/hide] [link to here]


V80 (0): V1:LSC_MICH_SET_EN_TRIG_0 [click here to expand/hide] [link to here]


V81 (0): V1:LSC_MICH_SET_ENBL_0 [click here to expand/hide] [link to here]


V82 (0): V1:LSC_MICH_SET_CORR_FLT_0 [click here to expand/hide] [link to here]


V83 (0): V1:LSC_MICH_SET_CORR_CLIP_0 [click here to expand/hide] [link to here]


V84 (0): V1:LSC_MICH_NOISE_0 [click here to expand/hide] [link to here]


V85 (0): V1:LSC_MICH_FILTER_ENBL_0 [click here to expand/hide] [link to here]


V86 (0): V1:LSC_LSC_ARMS_ON_0 [click here to expand/hide] [link to here]


V87 (0): V1:LSC_GREEN_OFF_0 [click here to expand/hide] [link to here]


V88 (0): V1:LSC_GREEN_LOCK_CHECK_0 [click here to expand/hide] [link to here]


V89 (0): V1:LSC_GREEN_LOCK_0 [click here to expand/hide] [link to here]


V90 (0): V1:LSC_Etalon_Acl_elapsed_time_0 [click here to expand/hide] [link to here]


V91 (0): V1:LSC_ENABLE_0 [click here to expand/hide] [link to here]


V92 (0): V1:LSC_DRMI_TRIGGER_IN4_p_0 [click here to expand/hide] [link to here]


V93 (0): V1:LSC_DRMI_TRIGGER_IN4_0 [click here to expand/hide] [link to here]


V94 (0): V1:LSC_DRMI_TRIGGER_IN3_0 [click here to expand/hide] [link to here]


V95 (0): V1:LSC_DRMI_TRIGGER_IN2_0 [click here to expand/hide] [link to here]


V96 (0): V1:LSC_DRMI_TRIGGER_IN1_0 [click here to expand/hide] [link to here]


V97 (0): V1:LSC_DRMI_TRIGGER_IN_0 [click here to expand/hide] [link to here]


V98 (0): V1:LSC_DARM_TRIG_0 [click here to expand/hide] [link to here]


V99 (0): V1:LSC_DARM_NOISE_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr