VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:6 h, 39 min, 12 s
Processing Date:Thu Feb 13 16:29:13 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:821616 sec → 9.509 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:61913943
Number of raw clusters:133638
Number of active clusters:122170 (SNR > 5.000) 3933 (SNR > 8.000) 2303 (SNR > 10.000) 1250 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (821616 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 122170 clusters
V0 → V1:LSC_DARM_ERR_0, vetoed clusters: 8265 (6.765 %)
V1 → V1:LSC_DARM_INPUT_0, vetoed clusters: 8122 (6.648 %)
V2 → V1:LSC_DCP_DARM_CORR_FLT_LF_0, vetoed clusters: 7710 (6.311 %)
V3 → V1:LSC_DARM_CORR_raw_0, vetoed clusters: 7122 (5.830 %)
V4 → V1:LSC_DCP_DARM_ERR_FLT_HF_0, vetoed clusters: 7004 (5.733 %)
V5 → V1:LSC_DCP_DARM_ERR_FLT_HF_DEL_0, vetoed clusters: 6811 (5.575 %)
V6 → V1:LSC_DCP_DARM_ERR_FLT_LF_0, vetoed clusters: 6187 (5.064 %)
V7 → V1:LSC_DCP_DARM_ERR_FLT_LF_DEL_0, vetoed clusters: 6099 (4.992 %)
V8 → V1:LSC_DCP_MM_RE_0, vetoed clusters: 1969 (1.612 %)
V9 → V1:LSC_NE_CORR_0, vetoed clusters: 1648 (1.349 %)

V0: V1:LSC_DARM_ERR_0 (ε = 6.765%, ε/d = 181.194) [click here to expand/hide] [link to here]


V1: V1:LSC_DARM_INPUT_0 (ε = 6.648%, ε/d = 183.341) [click here to expand/hide] [link to here]


V2: V1:LSC_DCP_DARM_CORR_FLT_LF_0 (ε = 6.311%, ε/d = 185.752) [click here to expand/hide] [link to here]


V3: V1:LSC_DARM_CORR_raw_0 (ε = 5.830%, ε/d = 206.687) [click here to expand/hide] [link to here]


V4: V1:LSC_DCP_DARM_ERR_FLT_HF_0 (ε = 5.733%, ε/d = 200.924) [click here to expand/hide] [link to here]


V5: V1:LSC_DCP_DARM_ERR_FLT_HF_DEL_0 (ε = 5.575%, ε/d = 203.641) [click here to expand/hide] [link to here]


V6: V1:LSC_DCP_DARM_ERR_FLT_LF_0 (ε = 5.064%, ε/d = 214.492) [click here to expand/hide] [link to here]


V7: V1:LSC_DCP_DARM_ERR_FLT_LF_DEL_0 (ε = 4.992%, ε/d = 217.256) [click here to expand/hide] [link to here]


V8: V1:LSC_DCP_MM_RE_0 (ε = 1.612%, ε/d = 557.186) [click here to expand/hide] [link to here]


V9: V1:LSC_NE_CORR_0 (ε = 1.349%, ε/d = 688.694) [click here to expand/hide] [link to here]


V10: V1:LSC_NI_CORR_0 (ε = 1.341%, ε/d = 686.167) [click here to expand/hide] [link to here]


V11: V1:LSC_DCP_DARM_CORR_FLT_HF_0 (ε = 1.286%, ε/d = 616.708) [click here to expand/hide] [link to here]


V12: V1:LSC_DCP_NORM_0 (ε = 1.235%, ε/d = 597.986) [click here to expand/hide] [link to here]


V13: V1:LSC_DCP_MM_IM_0 (ε = 1.199%, ε/d = 599.349) [click here to expand/hide] [link to here]


V14: V1:LSC_PR_CORR_0 (ε = 0.196%, ε/d = 713.067) [click here to expand/hide] [link to here]


V15: V1:LSC_PRCL_0 (ε = 0.190%, ε/d = 743.145) [click here to expand/hide] [link to here]


V16: V1:LSC_PRCL_ERR_0 (ε = 0.190%, ε/d = 743.145) [click here to expand/hide] [link to here]


V17: V1:LSC_PRCL_INPUT_0 (ε = 0.190%, ε/d = 743.145) [click here to expand/hide] [link to here]


V18: V1:LSC_PRCL_DARM_flt_0 (ε = 0.183%, ε/d = 718.007) [click here to expand/hide] [link to here]


V19: V1:LSC_PRCL_CORR_0 (ε = 0.167%, ε/d = 744.138) [click here to expand/hide] [link to here]


V20: V1:LSC_PRCL_CORR_raw_0 (ε = 0.167%, ε/d = 744.138) [click here to expand/hide] [link to here]


V21: V1:LSC_MICH_0 (ε = 0.092%, ε/d = 751.870) [click here to expand/hide] [link to here]


V22: V1:LSC_MICH_ERR_0 (ε = 0.092%, ε/d = 751.870) [click here to expand/hide] [link to here]


V23: V1:LSC_MICH_INPUT_0 (ε = 0.092%, ε/d = 751.870) [click here to expand/hide] [link to here]


V24: V1:LSC_MICH_SET_CORR_0 (ε = 0.080%, ε/d = 477.067) [click here to expand/hide] [link to here]


V25: V1:LSC_MICH_SET_IN_0 (ε = 0.080%, ε/d = 477.067) [click here to expand/hide] [link to here]


V26: V1:LSC_MICH_CORR_0 (ε = 0.073%, ε/d = 577.576) [click here to expand/hide] [link to here]


V27: V1:LSC_MICH_DARM_CORR_0 (ε = 0.073%, ε/d = 579.507) [click here to expand/hide] [link to here]


V28: V1:LSC_MICH_DARM_flt_0 (ε = 0.073%, ε/d = 579.507) [click here to expand/hide] [link to here]


V29: V1:LSC_MICH_SET_INPUT_0 (ε = 0.065%, ε/d = 465.419) [click here to expand/hide] [link to here]


V30: V1:LSC_SRCL_CORR_0 (ε = 0.063%, ε/d = 701.989) [click here to expand/hide] [link to here]


V31: V1:LSC_SRCL_0 (ε = 0.043%, ε/d = 743.844) [click here to expand/hide] [link to here]


V32: V1:LSC_SRCL_ERR_0 (ε = 0.043%, ε/d = 743.844) [click here to expand/hide] [link to here]


V33: V1:LSC_SRCL_INPUT_0 (ε = 0.043%, ε/d = 743.844) [click here to expand/hide] [link to here]


V34: V1:LSC_SRCL_DARM_flt_0 (ε = 0.012%, ε/d = 603.274) [click here to expand/hide] [link to here]


V35: V1:LSC_DARM_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V36: V1:LSC_DARM_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V37: V1:LSC_DRMI_TRIGGER_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:LSC_DRMI_TRIGGER_IN1_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:LSC_DRMI_TRIGGER_IN2_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:LSC_DRMI_TRIGGER_IN3_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:LSC_DRMI_TRIGGER_IN4_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:LSC_DRMI_TRIGGER_IN4_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:LSC_ENABLE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:LSC_Etalon_Acl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:LSC_GREEN_LOCK_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:LSC_GREEN_LOCK_CHECK_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:LSC_GREEN_OFF_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:LSC_LSC_ARMS_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:LSC_MICH_FILTER_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:LSC_MICH_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:LSC_MICH_SET_CORR_CLIP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:LSC_MICH_SET_CORR_FLT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:LSC_MICH_SET_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:LSC_MICH_SET_EN_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:LSC_MICH_SET_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:LSC_MICH_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:LSC_MICH_TRIGGER_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:LSC_MICH_TRIGGER_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:LSC_NArm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:LSC_NArm_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:LSC_NArm_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:LSC_NArm_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:LSC_NArm_LOCK_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:LSC_NArm_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:LSC_NArm_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:LSC_NE_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:LSC_NE_VIOLIN1_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:LSC_NE_VIOLIN2_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:LSC_NE_VIOLIN3_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:LSC_NE_VIOLIN4_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:LSC_NE_VIOLIN5_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:LSC_NE_VIOLIN6_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:LSC_NE_VIOLIN7_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:LSC_NE_VIOLIN8_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:LSC_NE_VIOLIN_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:LSC_NI_HB_moni_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:LSC_NI_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:LSC_NI_VIOLIN1_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:LSC_NI_VIOLIN2_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:LSC_NI_VIOLIN3_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:LSC_NI_VIOLIN4_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:LSC_NI_VIOLIN5_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:LSC_NI_VIOLIN6_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:LSC_NI_VIOLIN7_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:LSC_NI_VIOLIN8_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:LSC_NI_VIOLIN_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:LSC_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:LSC_PRCL_DARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:LSC_PRCL_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:LSC_PRCL_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:LSC_PRCL_TRIGGER_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:LSC_PRCL_TRIGGER_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:LSC_PR_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:LSC_SRCL_DARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:LSC_SRCL_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:LSC_SRCL_SET_CORR_CLIP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:LSC_SRCL_SET_CORR_FLT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:LSC_SRCL_SET_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:LSC_SRCL_SET_EN_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr