UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:2 h, 15 min, 13 s
Processing Date:Fri Feb 21 14:16:39 2025 (UTC)
Requested start:1407499998 → Mon Aug 12 12:13:00 2024 (UTC)
Requested stop:1408708852 → Mon Aug 26 12:00:34 2024 (UTC)
Requested livetime:950208 sec → 10.998 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 6.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (153): V1:Sc_MC_MIR_VOUT_D_0 [click here to expand/hide] [link to here]


V1 (146): V1:Sc_IB_INJ_RFC_PWR_0 [click here to expand/hide] [link to here]


V2 (142): V1:Sc_MC_MIR_VOUT_U_0 [click here to expand/hide] [link to here]


V3 (142): V1:Sc_MC_MIR_VOUT_L_0 [click here to expand/hide] [link to here]


V4 (141): V1:Sc_MC_MIR_VOUT_R_0 [click here to expand/hide] [link to here]


V5 (137): V1:Sc_MC_MIR_TY_0 [click here to expand/hide] [link to here]


V6 (137): V1:Sc_MC_MIR_PSDF_X1_0 [click here to expand/hide] [link to here]


V7 (136): V1:Sc_MC_MIR_PSDF_X2_0 [click here to expand/hide] [link to here]


V8 (130): V1:Sc_MC_MAR_TX_CORR_0 [click here to expand/hide] [link to here]


V9 (130): V1:Sc_MC_INJ_ty_p_0 [click here to expand/hide] [link to here]


V10 (130): V1:Sc_MC_INJ_tx_p_0 [click here to expand/hide] [link to here]


V11 (129): V1:Sc_IB_INJ_tz_0 [click here to expand/hide] [link to here]


V12 (127): V1:Sc_MC_AAOn_p_0 [click here to expand/hide] [link to here]


V13 (126): V1:Sc_MC_INJ_tx_0 [click here to expand/hide] [link to here]


V14 (126): V1:Sc_IB_MC_TX_0 [click here to expand/hide] [link to here]


V15 (120): V1:Sc_MC_MIR_TX_0 [click here to expand/hide] [link to here]


V16 (119): V1:Sc_MC_MIR_PSDF_Y2_0 [click here to expand/hide] [link to here]


V17 (104): V1:Sc_MC_MIR_PSDF_Y1_0 [click here to expand/hide] [link to here]


V18 (94): V1:Sc_IB_INJ_tx_0 [click here to expand/hide] [link to here]


V19 (81): V1:Sc_IB_MAR_TX_CORR_0 [click here to expand/hide] [link to here]


V20 (23): V1:Sc_BS_fModErr_0 [click here to expand/hide] [link to here]


V21 (22): V1:Sc_IB_MAR_TZ_CORR_0 [click here to expand/hide] [link to here]


V22 (19): V1:Sc_BS_MIR_VOUT_DL_0 [click here to expand/hide] [link to here]


V23 (18): V1:Sc_BS_MIR_VOUT_UR_0 [click here to expand/hide] [link to here]


V24 (16): V1:Sc_BS_MIR_Z_CORR_LN_0 [click here to expand/hide] [link to here]


V25 (16): V1:Sc_BS_MIR_Z_CORR_0 [click here to expand/hide] [link to here]


V26 (16): V1:Sc_BS_MIR_VOUT_UL_0 [click here to expand/hide] [link to here]


V27 (16): V1:Sc_BS_MIR_VOUT_DR_0 [click here to expand/hide] [link to here]


V28 (15): V1:Sc_IB_IMC_Tra_0 [click here to expand/hide] [link to here]


V29 (11): V1:Sc_IB_MAR_TY_CORR_0 [click here to expand/hide] [link to here]


V30 (0): V1:Sc_MC_MIR_Z_0 [click here to expand/hide] [link to here]


V31 (0): V1:Sc_MC_MIR_TY_CORR_0 [click here to expand/hide] [link to here]


V32 (0): V1:Sc_MC_MIR_TX_CORR_0 [click here to expand/hide] [link to here]


V33 (0): V1:Sc_MC_MIR_PSDTI_Y2_0 [click here to expand/hide] [link to here]


V34 (0): V1:Sc_MC_MIR_PSDTI_Y1_0 [click here to expand/hide] [link to here]


V35 (0): V1:Sc_MC_MIR_PSDTI_X2_0 [click here to expand/hide] [link to here]


V36 (0): V1:Sc_MC_MIR_PSDTI_X1_0 [click here to expand/hide] [link to here]


V37 (0): V1:Sc_MC_MIR_PSDTI_PWR_0 [click here to expand/hide] [link to here]


V38 (0): V1:Sc_MC_MIR_PSDTF_Y2_0 [click here to expand/hide] [link to here]


V39 (0): V1:Sc_MC_MIR_PSDTF_Y1_0 [click here to expand/hide] [link to here]


V40 (0): V1:Sc_MC_MIR_PSDTF_X2_0 [click here to expand/hide] [link to here]


V41 (0): V1:Sc_MC_MIR_PSDTF_X1_0 [click here to expand/hide] [link to here]


V42 (0): V1:Sc_MC_MIR_PSDTF_PWR_0 [click here to expand/hide] [link to here]


V43 (0): V1:Sc_MC_MIR_PSDI_Y2_0 [click here to expand/hide] [link to here]


V44 (0): V1:Sc_MC_MIR_PSDI_Y1_0 [click here to expand/hide] [link to here]


V45 (0): V1:Sc_MC_MIR_PSDI_X2_0 [click here to expand/hide] [link to here]


V46 (0): V1:Sc_MC_MIR_PSDI_X1_0 [click here to expand/hide] [link to here]


V47 (0): V1:Sc_MC_MIR_PSDI_PWR_0 [click here to expand/hide] [link to here]


V48 (0): V1:Sc_MC_MIR_PSDF_PWR_0 [click here to expand/hide] [link to here]


V49 (0): V1:Sc_MC_MIR_COIL_FLAG_0 [click here to expand/hide] [link to here]


V50 (0): V1:Sc_MC_MAR_Z_CORR_0 [click here to expand/hide] [link to here]


V51 (0): V1:Sc_MC_MAR_TZ_CORR_0 [click here to expand/hide] [link to here]


V52 (0): V1:Sc_MC_MAR_TY_CTRL_0 [click here to expand/hide] [link to here]


V53 (0): V1:Sc_MC_MAR_TY_CORR_0 [click here to expand/hide] [link to here]


V54 (0): V1:Sc_MC_MAR_TX_CTRL_0 [click here to expand/hide] [link to here]


V55 (0): V1:Sc_MC_MAR_COIL_FLAG_0 [click here to expand/hide] [link to here]


V56 (0): V1:Sc_MC_INJ_ty_0 [click here to expand/hide] [link to here]


V57 (0): V1:Sc_IB_noise_0 [click here to expand/hide] [link to here]


V58 (0): V1:Sc_IB_MAR_TZ_PM_0 [click here to expand/hide] [link to here]


V59 (0): V1:Sc_IB_MAR_TZ_0 [click here to expand/hide] [link to here]


V60 (0): V1:Sc_IB_MAR_TY_T_0 [click here to expand/hide] [link to here]


V61 (0): V1:Sc_IB_MAR_TY_PM_0 [click here to expand/hide] [link to here]


V62 (0): V1:Sc_IB_MAR_TX_PM_0 [click here to expand/hide] [link to here]


V63 (0): V1:Sc_IB_MAR_PSDT_Y2_0 [click here to expand/hide] [link to here]


V64 (0): V1:Sc_IB_MAR_PSDT_Y1_0 [click here to expand/hide] [link to here]


V65 (0): V1:Sc_IB_MAR_PSDT_X2_0 [click here to expand/hide] [link to here]


V66 (0): V1:Sc_IB_MAR_PSDT_X1_0 [click here to expand/hide] [link to here]


V67 (0): V1:Sc_IB_MAR_PSDT_PWR_0 [click here to expand/hide] [link to here]


V68 (0): V1:Sc_IB_MAR_COIL_FLAG_0 [click here to expand/hide] [link to here]


V69 (0): V1:Sc_IB_INJ_ty_0 [click here to expand/hide] [link to here]


V70 (0): V1:Sc_IB_BPCtyD_0 [click here to expand/hide] [link to here]


V71 (0): V1:Sc_IB_BPCtxD_0 [click here to expand/hide] [link to here]


V72 (0): V1:Sc_IB_BENCH_Z_0 [click here to expand/hide] [link to here]


V73 (0): V1:Sc_IB_BENCH_TY_0 [click here to expand/hide] [link to here]


V74 (0): V1:Sc_IB_BENCH_TX_0 [click here to expand/hide] [link to here]


V75 (0): V1:Sc_IB_BENCH_PSDI_Y2_0 [click here to expand/hide] [link to here]


V76 (0): V1:Sc_IB_BENCH_PSDI_Y1_0 [click here to expand/hide] [link to here]


V77 (0): V1:Sc_IB_BENCH_PSDI_X2_0 [click here to expand/hide] [link to here]


V78 (0): V1:Sc_IB_BENCH_PSDI_X1_0 [click here to expand/hide] [link to here]


V79 (0): V1:Sc_IB_BENCH_PSDI_PWR_0 [click here to expand/hide] [link to here]


V80 (0): V1:Sc_IB_BENCH_PSDF_Y2_0 [click here to expand/hide] [link to here]


V81 (0): V1:Sc_IB_BENCH_PSDF_Y1_0 [click here to expand/hide] [link to here]


V82 (0): V1:Sc_IB_BENCH_PSDF_X2_0 [click here to expand/hide] [link to here]


V83 (0): V1:Sc_IB_BENCH_PSDF_X1_0 [click here to expand/hide] [link to here]


V84 (0): V1:Sc_IB_BENCH_PSDF_PWR_0 [click here to expand/hide] [link to here]


V85 (0): V1:Sc_IB_AAsw_0 [click here to expand/hide] [link to here]


V86 (0): V1:Sc_BS_noise_0 [click here to expand/hide] [link to here]


V87 (0): V1:Sc_BS_MIR_Z_0 [click here to expand/hide] [link to here]


V88 (0): V1:Sc_BS_MIR_TY_AA_0 [click here to expand/hide] [link to here]


V89 (0): V1:Sc_BS_MIR_TY_0 [click here to expand/hide] [link to here]


V90 (0): V1:Sc_BS_MIR_TX_AA_0 [click here to expand/hide] [link to here]


V91 (0): V1:Sc_BS_MIR_TX_0 [click here to expand/hide] [link to here]


V92 (0): V1:Sc_BS_MIR_PSDI_Y2_0 [click here to expand/hide] [link to here]


V93 (0): V1:Sc_BS_MIR_PSDI_X2_0 [click here to expand/hide] [link to here]


V94 (0): V1:Sc_BS_MIR_PSDI_PWR_0 [click here to expand/hide] [link to here]


V95 (0): V1:Sc_BS_MIR_PSDF_Y2_0 [click here to expand/hide] [link to here]


V96 (0): V1:Sc_BS_MIR_PSDF_Y1_0 [click here to expand/hide] [link to here]


V97 (0): V1:Sc_BS_MIR_PSDF_X2_0 [click here to expand/hide] [link to here]


V98 (0): V1:Sc_BS_MIR_PSDF_X1_0 [click here to expand/hide] [link to here]


V99 (0): V1:Sc_BS_MIR_PSDF_PWR_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr