UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:3 h, 18 min, 39 s
Processing Date:Fri Feb 21 15:20:02 2025 (UTC)
Requested start:1407499998 → Mon Aug 12 12:13:00 2024 (UTC)
Requested stop:1408708852 → Mon Aug 26 12:00:34 2024 (UTC)
Requested livetime:950208 sec → 10.998 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 6.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (2519): V1:LSC_DARM_ERR_0 [click here to expand/hide] [link to here]


V1 (2510): V1:LSC_DARM_0 [click here to expand/hide] [link to here]


V2 (2501): V1:LSC_B1_DC_0 [click here to expand/hide] [link to here]


V3 (2483): V1:LSC_B1_DC_IN1_0 [click here to expand/hide] [link to here]


V4 (2205): V1:LSC_DARM_INPUT_0 [click here to expand/hide] [link to here]


V5 (2111): V1:LSC_B1_DC_INPUT_0 [click here to expand/hide] [link to here]


V6 (2111): V1:LSC_B1_DC_IN2_0 [click here to expand/hide] [link to here]


V7 (2068): V1:LSC_DARM_CORR_raw_0 [click here to expand/hide] [link to here]


V8 (2027): V1:LSC_DCP_DARM_CORR_FLT_LF_0 [click here to expand/hide] [link to here]


V9 (1157): V1:LSC_DCP_DARM_CORR_FLT_HF_0 [click here to expand/hide] [link to here]


V10 (1019): V1:LSC_DARM_CORR_0 [click here to expand/hide] [link to here]


V11 (153): V1:INJ_SSFS_err_0 [click here to expand/hide] [link to here]


V12 (148): V1:INJ_RFC_TRA_DC_0 [click here to expand/hide] [link to here]


V13 (146): V1:INJ_RFC_TRA_0 [click here to expand/hide] [link to here]


V14 (17): V1:LSC_BS_CORR_0 [click here to expand/hide] [link to here]


V15 (16): V1:LSC_CARM_MC_INPUT_0 [click here to expand/hide] [link to here]


V16 (16): V1:LSC_CARM_MC_ERR_0 [click here to expand/hide] [link to here]


V17 (0): V1:LSC_DARM_TRIG_0 [click here to expand/hide] [link to here]


V18 (0): V1:LSC_DARM_NOISE_0 [click here to expand/hide] [link to here]


V19 (0): V1:LSC_CARM_TRIG_0 [click here to expand/hide] [link to here]


V20 (0): V1:LSC_CARM_SLOW_TRIG_0 [click here to expand/hide] [link to here]


V21 (0): V1:LSC_CARM_SLOW_ERR_0 [click here to expand/hide] [link to here]


V22 (0): V1:LSC_CARM_SLOW_CORR_0 [click here to expand/hide] [link to here]


V23 (0): V1:LSC_CARM_SLOW_0 [click here to expand/hide] [link to here]


V24 (0): V1:LSC_CARM_NOISE_0 [click here to expand/hide] [link to here]


V25 (0): V1:LSC_CARM_INPUT_0 [click here to expand/hide] [link to here]


V26 (0): V1:LSC_CARM_FAST_CORR_0 [click here to expand/hide] [link to here]


V27 (0): V1:LSC_CARM_ERR_0 [click here to expand/hide] [link to here]


V28 (0): V1:LSC_CARM_DARM_flt_0 [click here to expand/hide] [link to here]


V29 (0): V1:LSC_CARM_DARM_ON_0 [click here to expand/hide] [link to here]


V30 (0): V1:LSC_CARM_DARM_CORR_0 [click here to expand/hide] [link to here]


V31 (0): V1:LSC_CARM_CORR_0 [click here to expand/hide] [link to here]


V32 (0): V1:LSC_CARM_0 [click here to expand/hide] [link to here]


V33 (0): V1:LSC_BS_LOCK_FLAG_0 [click here to expand/hide] [link to here]


V34 (0): V1:LSC_Acl_elapsed_time_0 [click here to expand/hide] [link to here]


V35 (0): V1:LSC_Acl_Moni_elapsed_time_0 [click here to expand/hide] [link to here]


V36 (0): V1:LSC_Acl_Moni_CfgChange_0 [click here to expand/hide] [link to here]


V37 (0): V1:LSC_Acl_CfgChange_0 [click here to expand/hide] [link to here]


V38 (0): V1:LSC_ARMS_LOCK_ON_0 [click here to expand/hide] [link to here]


V39 (0): V1:LNFS_RAMS_elapsed_time_0 [click here to expand/hide] [link to here]


V40 (0): V1:LNFS_RAMS_CfgChange_0 [click here to expand/hide] [link to here]


V41 (0): V1:LNFS_Demod_elapsed_time_0 [click here to expand/hide] [link to here]


V42 (0): V1:LNFS_Demod_CfgChange_0 [click here to expand/hide] [link to here]


V43 (0): V1:LFC_Z_SC_ERR_0 [click here to expand/hide] [link to here]


V44 (0): V1:LFC_Z_PRE_0 [click here to expand/hide] [link to here]


V45 (0): V1:LFC_Z_GR_ERR_0 [click here to expand/hide] [link to here]


V46 (0): V1:LFC_Z_CORR_ENB_0 [click here to expand/hide] [link to here]


V47 (0): V1:LFC_Z_CORR_0 [click here to expand/hide] [link to here]


V48 (0): V1:LFC_SC_PD_RF_11MHz_I_FIL_0 [click here to expand/hide] [link to here]


V49 (0): V1:LFC_SC_PD_RF_11MHz_I_CAL_0 [click here to expand/hide] [link to here]


V50 (0): V1:LFC_SC_PD_DC_0 [click here to expand/hide] [link to here]


V51 (0): V1:LFC_NOISE_0 [click here to expand/hide] [link to here]


V52 (0): V1:LFC_LOCK_FLAG_0 [click here to expand/hide] [link to here]


V53 (0): V1:LFC_GR_PD_RF_5MHz_I_NORM_0 [click here to expand/hide] [link to here]


V54 (0): V1:LFC_GR_PD_RF_5MHz_I_FIL_0 [click here to expand/hide] [link to here]


V55 (0): V1:LFC_GR_PD_RF_5MHz_I_CAL_0 [click here to expand/hide] [link to here]


V56 (0): V1:LFC_GR_PD_RF_5MHz_I_0 [click here to expand/hide] [link to here]


V57 (0): V1:LFC_Ctrl_elapsed_time_0 [click here to expand/hide] [link to here]


V58 (0): V1:LFC_Ctrl_CfgChange_0 [click here to expand/hide] [link to here]


V59 (0): V1:LFC_AOM_LOOP_SET_1kHz_0 [click here to expand/hide] [link to here]


V60 (0): V1:LFC_AOM_LOOP_PRE_1kHz_0 [click here to expand/hide] [link to here]


V61 (0): V1:LFC_AOM_LOOP_POST_1kHz_0 [click here to expand/hide] [link to here]


V62 (0): V1:LFC_AOM_LOOP_INPUT_1kHz_0 [click here to expand/hide] [link to here]


V63 (0): V1:LFC_AOM_LOOP_GAIN_1kHz_0 [click here to expand/hide] [link to here]


V64 (0): V1:LFC_AOM_LOOP_ENBL_1kHz_0 [click here to expand/hide] [link to here]


V65 (0): V1:LFC_AOM_LOOP_DC2_sw_1kHz_0 [click here to expand/hide] [link to here]


V66 (0): V1:LFC_AOM_LOOP_DC1_sw_1kHz_0 [click here to expand/hide] [link to here]


V67 (0): V1:LFC_AOM_LOOP_CORR_1kHz_0 [click here to expand/hide] [link to here]


V68 (0): V1:LFC_AOM_LOOP_CORR_0 [click here to expand/hide] [link to here]


V69 (0): V1:ISYSnoise_elapsed_time_0 [click here to expand/hide] [link to here]


V70 (0): V1:ISYSnoise_CfgChange_0 [click here to expand/hide] [link to here]


V71 (0): V1:ISYS_slow_pre_elapsed_time_0 [click here to expand/hide] [link to here]


V72 (0): V1:ISYS_slow_pre_CfgChange_0 [click here to expand/hide] [link to here]


V73 (0): V1:ISYS_slow_elapsed_time_0 [click here to expand/hide] [link to here]


V74 (0): V1:ISYS_moni_elapsed_time_0 [click here to expand/hide] [link to here]


V75 (0): V1:ISYS_moni_CfgChange_0 [click here to expand/hide] [link to here]


V76 (0): V1:ISYS_EER_dac_elapsed_time_0 [click here to expand/hide] [link to here]


V77 (0): V1:ISYS_EER_dac_CfgChange_0 [click here to expand/hide] [link to here]


V78 (0): V1:ISYS_EER_FastDac_elapsed_time_0 [click here to expand/hide] [link to here]


V79 (0): V1:ISYS_EER_FastDac_CfgChange_0 [click here to expand/hide] [link to here]


V80 (0): V1:ISYS_Acl_elapsed_time_0 [click here to expand/hide] [link to here]


V81 (0): V1:ISYS_Acl_CfgChange_0 [click here to expand/hide] [link to here]


V82 (0): V1:ISC_Tpro_processed_packets_0 [click here to expand/hide] [link to here]


V83 (0): V1:ISC_Tpro_elapsed_time_0 [click here to expand/hide] [link to here]


V84 (0): V1:ISC_LASER_AUX_test_0 [click here to expand/hide] [link to here]


V85 (0): V1:INJ_Tpro_processed_packets_0 [click here to expand/hide] [link to here]


V86 (0): V1:INJ_Tpro_elapsed_time_0 [click here to expand/hide] [link to here]


V87 (0): V1:INJ_SSFS_LOCK_ON_0 [click here to expand/hide] [link to here]


V88 (0): V1:INJ_SSFS_BOOST_TRIG_0 [click here to expand/hide] [link to here]


V89 (0): V1:INJ_SSFS_BOOST_ON_0 [click here to expand/hide] [link to here]


V90 (0): V1:INJ_SL_NOISE_0 [click here to expand/hide] [link to here]


V91 (0): V1:INJ_SIB2_RFC_6MHz_I_0 [click here to expand/hide] [link to here]


V92 (0): V1:INJ_SIB1_QD2_V_NORM_0 [click here to expand/hide] [link to here]


V93 (0): V1:INJ_SIB1_QD2_H_NORM_0 [click here to expand/hide] [link to here]


V94 (0): V1:INJ_SIB1_QD1_V_NORM_0 [click here to expand/hide] [link to here]


V95 (0): V1:INJ_SIB1_QD1_H_NORM_0 [click here to expand/hide] [link to here]


V96 (0): V1:INJ_SFP_B4_RAMP_0 [click here to expand/hide] [link to here]


V97 (0): V1:INJ_PStabErr_0 [click here to expand/hide] [link to here]


V98 (0): V1:INJ_PStabCorr_tempOffset_0 [click here to expand/hide] [link to here]


V99 (0): V1:INJ_PStabCorr_tempHP_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr