UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:0 h, 24 min, 12 s
Processing Date:Fri Feb 21 12:25:35 2025 (UTC)
Requested start:1407499998 → Mon Aug 12 12:13:00 2024 (UTC)
Requested stop:1408708852 → Mon Aug 26 12:00:34 2024 (UTC)
Requested livetime:950208 sec → 10.998 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 6.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (109): V1:ASC_B2_QD1_H_0 [click here to expand/hide] [link to here]


V1 (48): V1:ASC_B1p_QD1_H_0 [click here to expand/hide] [link to here]


V2 (38): V1:ASC_B1p_QD2_H_0 [click here to expand/hide] [link to here]


V3 (15): V1:ASC_B1p_QD1_V_0 [click here to expand/hide] [link to here]


V4 (0): V1:ASC_B2_QD2_18MHz_V_Q_0 [click here to expand/hide] [link to here]


V5 (0): V1:ASC_B2_QD2_18MHz_V_I_NORM_0 [click here to expand/hide] [link to here]


V6 (0): V1:ASC_B2_QD2_18MHz_V_I_0 [click here to expand/hide] [link to here]


V7 (0): V1:ASC_B2_QD2_18MHz_H_Q_0 [click here to expand/hide] [link to here]


V8 (0): V1:ASC_B2_QD2_18MHz_H_I_NORM_0 [click here to expand/hide] [link to here]


V9 (0): V1:ASC_B2_QD2_18MHz_H_I_0 [click here to expand/hide] [link to here]


V10 (0): V1:ASC_B2_QD2_14MHz_V_Q_0 [click here to expand/hide] [link to here]


V11 (0): V1:ASC_B2_QD2_14MHz_V_I_0 [click here to expand/hide] [link to here]


V12 (0): V1:ASC_B2_QD2_14MHz_H_Q_0 [click here to expand/hide] [link to here]


V13 (0): V1:ASC_B2_QD2_14MHz_H_I_0 [click here to expand/hide] [link to here]


V14 (0): V1:ASC_B2_QD1_V_0 [click here to expand/hide] [link to here]


V15 (0): V1:ASC_B2_QD1_Sum_0 [click here to expand/hide] [link to here]


V16 (0): V1:ASC_B2_QD1_8MHz_V_Q_0 [click here to expand/hide] [link to here]


V17 (0): V1:ASC_B2_QD1_8MHz_V_I_0 [click here to expand/hide] [link to here]


V18 (0): V1:ASC_B2_QD1_8MHz_H_Q_0 [click here to expand/hide] [link to here]


V19 (0): V1:ASC_B2_QD1_8MHz_H_I_0 [click here to expand/hide] [link to here]


V20 (0): V1:ASC_B2_QD1_6MHz_V_Q_0 [click here to expand/hide] [link to here]


V21 (0): V1:ASC_B2_QD1_6MHz_V_I_0 [click here to expand/hide] [link to here]


V22 (0): V1:ASC_B2_QD1_6MHz_H_Q_0 [click here to expand/hide] [link to here]


V23 (0): V1:ASC_B2_QD1_6MHz_H_I_0 [click here to expand/hide] [link to here]


V24 (0): V1:ASC_B2_QD1_18MHz_V_Q_0 [click here to expand/hide] [link to here]


V25 (0): V1:ASC_B2_QD1_18MHz_V_I_0 [click here to expand/hide] [link to here]


V26 (0): V1:ASC_B2_QD1_18MHz_H_Q_0 [click here to expand/hide] [link to here]


V27 (0): V1:ASC_B2_QD1_18MHz_H_I_0 [click here to expand/hide] [link to here]


V28 (0): V1:ASC_B1p_QPD_TRIG_LO_0 [click here to expand/hide] [link to here]


V29 (0): V1:ASC_B1p_QPD_TRIG_HI_0 [click here to expand/hide] [link to here]


V30 (0): V1:ASC_B1p_QPD_TRIG_0 [click here to expand/hide] [link to here]


V31 (0): V1:ASC_B1p_QD_V_select_0 [click here to expand/hide] [link to here]


V32 (0): V1:ASC_B1p_QD_H_select_0 [click here to expand/hide] [link to here]


V33 (0): V1:ASC_B1p_QD2_V_scale_0 [click here to expand/hide] [link to here]


V34 (0): V1:ASC_B1p_QD2_V_0 [click here to expand/hide] [link to here]


V35 (0): V1:ASC_B1p_QD2_Sum_0 [click here to expand/hide] [link to here]


V36 (0): V1:ASC_B1p_QD2_H_scale_0 [click here to expand/hide] [link to here]


V37 (0): V1:ASC_B1p_QD2_56MHz_V_Q_0 [click here to expand/hide] [link to here]


V38 (0): V1:ASC_B1p_QD2_56MHz_V_I_NORM_0 [click here to expand/hide] [link to here]


V39 (0): V1:ASC_B1p_QD2_56MHz_V_I_0 [click here to expand/hide] [link to here]


V40 (0): V1:ASC_B1p_QD2_56MHz_H_Q_0 [click here to expand/hide] [link to here]


V41 (0): V1:ASC_B1p_QD2_56MHz_H_I_NORM_0 [click here to expand/hide] [link to here]


V42 (0): V1:ASC_B1p_QD2_56MHz_H_I_0 [click here to expand/hide] [link to here]


V43 (0): V1:ASC_B1p_QD2_50MHz_V_Q_0 [click here to expand/hide] [link to here]


V44 (0): V1:ASC_B1p_QD2_50MHz_V_I_0 [click here to expand/hide] [link to here]


V45 (0): V1:ASC_B1p_QD2_50MHz_H_Q_0 [click here to expand/hide] [link to here]


V46 (0): V1:ASC_B1p_QD2_50MHz_H_I_0 [click here to expand/hide] [link to here]


V47 (0): V1:ASC_B1p_QD1_V_scale_0 [click here to expand/hide] [link to here]


V48 (0): V1:ASC_B1p_QD1_Sum_0 [click here to expand/hide] [link to here]


V49 (0): V1:ASC_B1p_QD1_H_scale_0 [click here to expand/hide] [link to here]


V50 (0): V1:ASC_B1p_QD1_50MHz_V_Q_0 [click here to expand/hide] [link to here]


V51 (0): V1:ASC_B1p_QD1_50MHz_V_I_0 [click here to expand/hide] [link to here]


V52 (0): V1:ASC_B1p_QD1_50MHz_H_Q_0 [click here to expand/hide] [link to here]


V53 (0): V1:ASC_B1p_QD1_50MHz_H_I_0 [click here to expand/hide] [link to here]


V54 (0): V1:ASC_B1QPD_TRIGGER_0 [click here to expand/hide] [link to here]


V55 (0): V1:ASC_Acl_elapsed_time_0 [click here to expand/hide] [link to here]


V56 (0): V1:ASC_Acl_CfgChange_0 [click here to expand/hide] [link to here]


V57 (0): V1:AFC_NF_PSD_Y_NORM_0 [click here to expand/hide] [link to here]


V58 (0): V1:AFC_NF_PSD_X_NORM_0 [click here to expand/hide] [link to here]


V59 (0): V1:AFC_GR_FCIM_AA_TY_SET_0 [click here to expand/hide] [link to here]


V60 (0): V1:AFC_GR_FCIM_AA_TY_PRE_0 [click here to expand/hide] [link to here]


V61 (0): V1:AFC_GR_FCIM_AA_TY_POST_0 [click here to expand/hide] [link to here]


V62 (0): V1:AFC_GR_FCIM_AA_TY_INPUT_0 [click here to expand/hide] [link to here]


V63 (0): V1:AFC_GR_FCIM_AA_TY_CORR_0 [click here to expand/hide] [link to here]


V64 (0): V1:AFC_GR_FCIM_AA_TY_0 [click here to expand/hide] [link to here]


V65 (0): V1:AFC_GR_FCIM_AA_TX_SET_0 [click here to expand/hide] [link to here]


V66 (0): V1:AFC_GR_FCIM_AA_TX_PRE_0 [click here to expand/hide] [link to here]


V67 (0): V1:AFC_GR_FCIM_AA_TX_POST_0 [click here to expand/hide] [link to here]


V68 (0): V1:AFC_GR_FCIM_AA_TX_INPUT_0 [click here to expand/hide] [link to here]


V69 (0): V1:AFC_GR_FCIM_AA_TX_CORR_0 [click here to expand/hide] [link to here]


V70 (0): V1:AFC_GR_FCIM_AA_TX_0 [click here to expand/hide] [link to here]


V71 (0): V1:AFC_GR_FCEM_AA_TY_SET_0 [click here to expand/hide] [link to here]


V72 (0): V1:AFC_GR_FCEM_AA_TY_PRE_0 [click here to expand/hide] [link to here]


V73 (0): V1:AFC_GR_FCEM_AA_TY_POST_0 [click here to expand/hide] [link to here]


V74 (0): V1:AFC_GR_FCEM_AA_TY_INPUT_0 [click here to expand/hide] [link to here]


V75 (0): V1:AFC_GR_FCEM_AA_TY_CORR_0 [click here to expand/hide] [link to here]


V76 (0): V1:AFC_GR_FCEM_AA_TY_0 [click here to expand/hide] [link to here]


V77 (0): V1:AFC_GR_FCEM_AA_TX_SET_0 [click here to expand/hide] [link to here]


V78 (0): V1:AFC_GR_FCEM_AA_TX_PRE_0 [click here to expand/hide] [link to here]


V79 (0): V1:AFC_GR_FCEM_AA_TX_POST_0 [click here to expand/hide] [link to here]


V80 (0): V1:AFC_GR_FCEM_AA_TX_INPUT_0 [click here to expand/hide] [link to here]


V81 (0): V1:AFC_GR_FCEM_AA_TX_CORR_0 [click here to expand/hide] [link to here]


V82 (0): V1:AFC_GR_FCEM_AA_TX_0 [click here to expand/hide] [link to here]


V83 (0): V1:AFC_GR_BPC_CTRL_ENBL_CORR_0 [click here to expand/hide] [link to here]


V84 (0): V1:AFC_GR_BPC_CTRL_ENBL_0 [click here to expand/hide] [link to here]


V85 (0): V1:AFC_GR_BPC2_ENBL_CORR_0 [click here to expand/hide] [link to here]


V86 (0): V1:AFC_GR_BPC2_ENBL_0 [click here to expand/hide] [link to here]


V87 (0): V1:AFC_GR_AA_NOISE_0 [click here to expand/hide] [link to here]


V88 (0): V1:AFC_GREEN_AA_ENBL_CORR_0 [click here to expand/hide] [link to here]


V89 (0): V1:AFC_GREEN_AA_ENBL_0 [click here to expand/hide] [link to here]


V90 (0): V1:AFC_FLT_CORR_FCIM_TY_0 [click here to expand/hide] [link to here]


V91 (0): V1:AFC_FLT_CORR_FCIM_TX_0 [click here to expand/hide] [link to here]


V92 (0): V1:AFC_FLT_CORR_FCEM_TY_0 [click here to expand/hide] [link to here]


V93 (0): V1:AFC_FLT_CORR_FCEM_TX_0 [click here to expand/hide] [link to here]


V94 (0): V1:AFC_FF_PSD_Y_NORM_0 [click here to expand/hide] [link to here]


V95 (0): V1:AFC_FF_PSD_X_NORM_0 [click here to expand/hide] [link to here]


V96 (0): V1:AFC_DRIFT_CTRL_ENBL_CORR_0 [click here to expand/hide] [link to here]


V97 (0): V1:AFC_DRIFT_CTRL_ENBL_0 [click here to expand/hide] [link to here]


V98 (0): V1:AFC_Ctrl_elapsed_time_0 [click here to expand/hide] [link to here]


V99 (0): V1:AFC_Ctrl_CfgChange_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr