VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:0 h, 18 min, 18 s
Processing Date:Thu Feb 13 10:08:18 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:821616 sec → 9.509 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:61913943
Number of raw clusters:133638
Number of active clusters:122170 (SNR > 5.000) 3933 (SNR > 8.000) 2303 (SNR > 10.000) 1250 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (821616 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 122170 clusters
V0 → V1:SPRB_B4_PD2_Audio_0, vetoed clusters: 177 (0.145 %)
V1 → V1:SPRB_B4_PD2_Blended_0, vetoed clusters: 174 (0.142 %)
V2 → V1:SPRB_B4_PD2_Blended_D_0, vetoed clusters: 173 (0.142 %)
V3 → V1:SPRB_B4_QD1_12MHz_Sum_0, vetoed clusters: 124 (0.101 %)
V4 → V1:SPRB_B4_QD2_12MHz_Sum_0, vetoed clusters: 116 (0.095 %)
V5 → V1:SPRB_B4_QD1_50MHz_SUM_Q_0, vetoed clusters: 101 (0.083 %)
V6 → V1:SPRB_B4_PD2_DC_0, vetoed clusters: 97 (0.079 %)
V7 → V1:SPRB_B4_QD2_50MHz_SUM_Q_0, vetoed clusters: 92 (0.075 %)
V8 → V1:SPRB_B4_QD2_6MHz_H_I_0, vetoed clusters: 83 (0.068 %)
V9 → V1:SPRB_B4_QD2_56MHz_H_I_0, vetoed clusters: 78 (0.064 %)

V0: V1:SPRB_B4_PD2_Audio_0 (ε = 0.145%, ε/d = 515.075) [click here to expand/hide] [link to here]


V1: V1:SPRB_B4_PD2_Blended_0 (ε = 0.142%, ε/d = 544.197) [click here to expand/hide] [link to here]


V2: V1:SPRB_B4_PD2_Blended_D_0 (ε = 0.142%, ε/d = 547.106) [click here to expand/hide] [link to here]


V3: V1:SPRB_B4_QD1_12MHz_Sum_0 (ε = 0.101%, ε/d = 1078.278) [click here to expand/hide] [link to here]


V4: V1:SPRB_B4_QD2_12MHz_Sum_0 (ε = 0.095%, ε/d = 1088.779) [click here to expand/hide] [link to here]


V5: V1:SPRB_B4_QD1_50MHz_SUM_Q_0 (ε = 0.083%, ε/d = 1150.873) [click here to expand/hide] [link to here]


V6: V1:SPRB_B4_PD2_DC_0 (ε = 0.079%, ε/d = 364.009) [click here to expand/hide] [link to here]


V7: V1:SPRB_B4_QD2_50MHz_SUM_Q_0 (ε = 0.075%, ε/d = 1252.666) [click here to expand/hide] [link to here]


V8: V1:SPRB_B4_QD2_6MHz_H_I_0 (ε = 0.068%, ε/d = 854.609) [click here to expand/hide] [link to here]


V9: V1:SPRB_B4_QD2_56MHz_H_I_0 (ε = 0.064%, ε/d = 1076.930) [click here to expand/hide] [link to here]


V10: V1:SPRB_B4_QD1_Sum_0 (ε = 0.061%, ε/d = 489.439) [click here to expand/hide] [link to here]


V11: V1:SPRB_B4_QD2_Sum_0 (ε = 0.053%, ε/d = 395.764) [click here to expand/hide] [link to here]


V12: V1:SPRB_B4_QD1_6MHz_H_I_0 (ε = 0.046%, ε/d = 647.830) [click here to expand/hide] [link to here]


V13: V1:SPRB_B4_QD2_56MHz_SUM_I_0 (ε = 0.043%, ε/d = 793.880) [click here to expand/hide] [link to here]


V14: V1:SPRB_B4_QD1_56MHz_SUM_I_0 (ε = 0.039%, ε/d = 655.852) [click here to expand/hide] [link to here]


V15: V1:SPRB_B4_QD1_6MHz_V_I_0 (ε = 0.038%, ε/d = 574.290) [click here to expand/hide] [link to here]


V16: V1:SPRB_B4_QD1_56MHz_V_Q_0 (ε = 0.036%, ε/d = 372.874) [click here to expand/hide] [link to here]


V17: V1:SPRB_B4_QD1_50MHz_SUM_I_0 (ε = 0.032%, ε/d = 1437.902) [click here to expand/hide] [link to here]


V18: V1:SPRB_B4_QD2_6MHz_V_Q_0 (ε = 0.031%, ε/d = 552.487) [click here to expand/hide] [link to here]


V19: V1:SPRB_B4_QD2_H_0 (ε = 0.030%, ε/d = 465.993) [click here to expand/hide] [link to here]


V20: V1:SPRB_B4_QD2_50MHz_SUM_I_0 (ε = 0.030%, ε/d = 2441.996) [click here to expand/hide] [link to here]


V21: V1:SPRB_B4_QD2_6MHz_V_I_0 (ε = 0.029%, ε/d = 546.207) [click here to expand/hide] [link to here]


V22: V1:SPRB_B4_QD2_56MHz_V_I_0 (ε = 0.029%, ε/d = 744.968) [click here to expand/hide] [link to here]


V23: V1:SPRB_B4_QD2_H_norm_0 (ε = 0.028%, ε/d = 1265.020) [click here to expand/hide] [link to here]


V24: V1:SPRB_B4_QD1_50MHz_H_I_0 (ε = 0.028%, ε/d = 1391.158) [click here to expand/hide] [link to here]


V25: V1:SPRB_B4_QD1_56MHz_SUM_Q_0 (ε = 0.027%, ε/d = 862.301) [click here to expand/hide] [link to here]


V26: V1:SPRB_B4_QD2_6MHz_SUM_I_0 (ε = 0.027%, ε/d = 1020.960) [click here to expand/hide] [link to here]


V27: V1:SPRB_B4_QD1_6MHz_SUM_Q_0 (ε = 0.026%, ε/d = 1119.564) [click here to expand/hide] [link to here]


V28: V1:SPRB_B4_QD2_6MHz_H_Q_0 (ε = 0.026%, ε/d = 1153.377) [click here to expand/hide] [link to here]


V29: V1:SPRB_B4_QD1_112MHz_Sum_0 (ε = 0.025%, ε/d = 660.497) [click here to expand/hide] [link to here]


V30: V1:SPRB_B4_QD2_6MHz_SUM_Q_0 (ε = 0.025%, ε/d = 1425.588) [click here to expand/hide] [link to here]


V31: V1:SPRB_B4_QD1_H_norm_0 (ε = 0.024%, ε/d = 427.397) [click here to expand/hide] [link to here]


V32: V1:SPRB_B4_QD2_V_norm_0 (ε = 0.024%, ε/d = 1340.404) [click here to expand/hide] [link to here]


V33: V1:SPRB_B4_QD1_56MHz_H_I_0 (ε = 0.024%, ε/d = 839.092) [click here to expand/hide] [link to here]


V34: V1:SPRB_B4_QD1_6MHz_V_Q_0 (ε = 0.021%, ε/d = 1221.095) [click here to expand/hide] [link to here]


V35: V1:SPRB_B4_QD1_56MHz_H_Q_0 (ε = 0.021%, ε/d = 930.063) [click here to expand/hide] [link to here]


V36: V1:SPRB_B4_QD1_56MHz_V_I_0 (ε = 0.020%, ε/d = 1136.862) [click here to expand/hide] [link to here]


V37: V1:SPRB_B4_QD2_56MHz_H_Q_0 (ε = 0.020%, ε/d = 5051.151) [click here to expand/hide] [link to here]


V38: V1:SPRB_B4_QD1_50MHz_H_Q_0 (ε = 0.020%, ε/d = 3654.662) [click here to expand/hide] [link to here]


V39: V1:SPRB_B4_QD2_112MHz_Sum_0 (ε = 0.020%, ε/d = 637.979) [click here to expand/hide] [link to here]


V40: V1:SPRB_B4_QD1_H_0 (ε = 0.019%, ε/d = 629.989) [click here to expand/hide] [link to here]


V41: V1:SPRB_B4_QD2_56MHz_V_Q_0 (ε = 0.016%, ε/d = 640.360) [click here to expand/hide] [link to here]


V42: V1:SPRB_B4_QD2_V_0 (ε = 0.013%, ε/d = 621.915) [click here to expand/hide] [link to here]


V43: V1:SPRB_B4_QD1_GALVO_V_CORR_0 (ε = 0.012%, ε/d = 2728.652) [click here to expand/hide] [link to here]


V44: V1:SPRB_B4_QD1_GALVO_V_CORR_notsafe_0 (ε = 0.012%, ε/d = 2728.652) [click here to expand/hide] [link to here]


V45: V1:SPRB_B4_QD2_50MHz_H_I_0 (ε = 0.011%, ε/d = 2314.782) [click here to expand/hide] [link to here]


V46: V1:SPRB_B4_QD1_50MHz_V_Q_0 (ε = 0.010%, ε/d = 2884.571) [click here to expand/hide] [link to here]


V47: V1:SPRB_B4_PD2_IBias_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:SPRB_B4_PD2_VBias_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:SPRB_B4_PD_select_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:SPRB_B4_QD1_112MHz_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:SPRB_B4_QD1_112MHz_H_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:SPRB_B4_QD1_112MHz_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:SPRB_B4_QD1_112MHz_V_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:SPRB_B4_QD1_12MHz_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:SPRB_B4_QD1_12MHz_H_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:SPRB_B4_QD1_12MHz_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:SPRB_B4_QD1_12MHz_V_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:SPRB_B4_QD1_50MHz_V_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:SPRB_B4_QD1_6MHz_H_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:SPRB_B4_QD1_6MHz_SUM_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:SPRB_B4_QD1_GALVO_H_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:SPRB_B4_QD1_GALVO_H_CORR_notsafe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:SPRB_B4_QD1_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:SPRB_B4_QD1_V_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:SPRB_B4_QD2_112MHz_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:SPRB_B4_QD2_112MHz_H_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:SPRB_B4_QD2_112MHz_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:SPRB_B4_QD2_112MHz_V_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:SPRB_B4_QD2_12MHz_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:SPRB_B4_QD2_12MHz_H_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:SPRB_B4_QD2_12MHz_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:SPRB_B4_QD2_12MHz_V_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:SPRB_B4_QD2_50MHz_H_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:SPRB_B4_QD2_50MHz_V_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:SPRB_B4_QD2_50MHz_V_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:SPRB_B4_QD2_56MHz_SUM_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:SPRB_B4_QD2_GALVO_H_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:SPRB_B4_QD2_GALVO_H_CORR_notsafe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:SPRB_B4_QD2_GALVO_V_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:SPRB_B4_QD2_GALVO_V_CORR_notsafe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:SPRB_Clock_100MHz_mag_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:SPRB_Clock_100MHz_phi_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:SPRB_GALVO_gene_sum_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:SPRB_LC_B4_QD2_TX_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:SPRB_LC_B4_QD2_TY_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:SPRB_LC_B4_QD2_enbl_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:SPRB_LC_B4_QD2_enbl_safe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:SPRB_LC_COIL_BL_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:SPRB_LC_COIL_BL_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:SPRB_LC_COIL_BR_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:SPRB_LC_COIL_BR_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:SPRB_LC_COIL_FL_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:SPRB_LC_COIL_FL_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:SPRB_LC_COIL_FR_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:SPRB_LC_COIL_FR_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:SPRB_LC_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:SPRB_LC_LVDT_BL_H_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:SPRB_LC_LVDT_BL_V_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:SPRB_LC_LVDT_BR_H_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr