Index of /frobinet/upv/1433251327.1433662380/report.32.64245073/V1:Hrec_hoft_16384Hz/
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V1:SIB2_B2_QD1_56MHz_SUM_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD1_56MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_56MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_56MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_6MHz_H_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_6MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_6MHz_SUM_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_6MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_6MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_6MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_8MHz_H_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_8MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_8MHz_SUM_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_8MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_8MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_8MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_GALVO_H_CORR_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD1_GALVO_H_CORR_notsafe_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD1_GALVO_V_CORR_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD1_GALVO_V_CORR_notsafe_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD1_H_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_H_norm_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_Sum_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_V_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD1_V_norm_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_14MHz_H_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_14MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_14MHz_SUM_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_14MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_14MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_14MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_16MHz_H_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_16MHz_H_norm_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_16MHz_Sum_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_16MHz_V_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_16MHz_V_norm_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_18MHz_H_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_18MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_18MHz_SUM_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_18MHz_SUM_Q_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_18MHz_V_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_18MHz_V_Q_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_2f_centering_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_48MHz_H_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_48MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_48MHz_SUM_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_48MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_48MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_48MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_56MHz_H_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_56MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_56MHz_SUM_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_56MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_56MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_56MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_6MHz_H_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_6MHz_H_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_6MHz_SUM_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_6MHz_SUM_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_6MHz_V_I_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_6MHz_V_Q_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_8MHz_H_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_8MHz_H_Q_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_8MHz_SUM_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_8MHz_SUM_Q_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_8MHz_V_I_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_8MHz_V_Q_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_GALVO_H_CORR_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_GALVO_H_CORR_notsafe_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_GALVO_V_CORR_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_GALVO_V_CORR_notsafe_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_H_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_H_norm_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_Sum_0/ 23-Jun-2025 10:31 -
V1:SIB2_B2_QD2_V_0/ 23-Jun-2025 10:30 -
V1:SIB2_B2_QD2_V_norm_0/ 23-Jun-2025 10:30 -
V1:SIB2_Clock_100MHz_mag_0/ 23-Jun-2025 10:30 -
V1:SIB2_Clock_100MHz_phi_0/ 23-Jun-2025 10:30 -
V1:SIB2_GALVO_gene_sum_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_B2_QD2_TX_err_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_B2_QD2_TY_err_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_B2_QD2_enbl_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_B2_QD2_enbl_safe_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_COIL_BL_H_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_COIL_BL_V_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_COIL_BR_H_0/ 23-Jun-2025 10:31 -
V1:SIB2_LC_COIL_BR_V_0/ 23-Jun-2025 10:31 -
V1:SIB2_LC_COIL_FL_H_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_COIL_FL_V_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_COIL_FR_H_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_COIL_FR_V_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_CfgChange_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_BL_H_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_BL_V_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_BR_H_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_BR_V_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_FL_H_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_FL_V_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_FR_H_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
V1:SIB2_LC_LVDT_FR_V_out_raw_1000Hz_0/ 23-Jun-2025 10:30 -
perf/ 23-Jun-2025 10:31 -