VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:0 h, 22 min, 13 s
Processing Date:Fri Jun 20 17:33:56 2025 (UTC)
Requested start:1433251331 → Fri Jun 6 13:21:53 2025 (UTC)
Requested stop:1433662376 → Wed Jun 11 07:32:38 2025 (UTC)
Requested livetime:256511 sec → 2.969 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:48226537
Number of raw clusters:34915
Number of active clusters:34915 (SNR > 5.000) 6124 (SNR > 8.000) 5110 (SNR > 10.000) 3304 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (256511 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 34915 clusters
V0 → V1:SDB2_CAL_B1p_PD1_Audio_10kHz_0, vetoed clusters: 326 (0.934 %)
V1 → V1:SDB2_CAL_B1p_PD1_Blended_10kHz_0, vetoed clusters: 325 (0.931 %)
V2 → V1:SDB2_POWERSUPPLY_DBOX_LEFT_DOWN_p12V_0, vetoed clusters: 159 (0.455 %)
V3 → V1:SDB2_B5_QD2_50MHz_H_Q_0, vetoed clusters: 42 (0.120 %)
V4 → V1:SDB2_B5_QD2_6MHz_SUM_Q_0, vetoed clusters: 41 (0.117 %)
V5 → V1:SDB2_B5_QD2_112MHz_V_norm_0, vetoed clusters: 37 (0.106 %)
V6 → V1:SDB2_B5_QD2_112MHz_Sum_0, vetoed clusters: 35 (0.100 %)
V7 → V1:SDB2_B5_QD2_112MHz_V_0, vetoed clusters: 35 (0.100 %)
V8 → V1:SDB2_B5_QD2_112MHz_H_norm_0, vetoed clusters: 30 (0.086 %)
V9 → V1:SDB2_B5_QD2_56MHz_H_Q_0, vetoed clusters: 26 (0.074 %)

V0: V1:SDB2_CAL_B1p_PD1_Audio_10kHz_0 (ε = 0.934%, ε/d = 81.454) [click here to expand/hide] [link to here]


V1: V1:SDB2_CAL_B1p_PD1_Blended_10kHz_0 (ε = 0.931%, ε/d = 82.009) [click here to expand/hide] [link to here]


V2: V1:SDB2_POWERSUPPLY_DBOX_LEFT_DOWN_p12V_0 (ε = 0.455%, ε/d = 77.303) [click here to expand/hide] [link to here]


V3: V1:SDB2_B5_QD2_50MHz_H_Q_0 (ε = 0.120%, ε/d = 15.925) [click here to expand/hide] [link to here]


V4: V1:SDB2_B5_QD2_6MHz_SUM_Q_0 (ε = 0.117%, ε/d = 17.747) [click here to expand/hide] [link to here]


V5: V1:SDB2_B5_QD2_112MHz_V_norm_0 (ε = 0.106%, ε/d = 15.162) [click here to expand/hide] [link to here]


V6: V1:SDB2_B5_QD2_112MHz_Sum_0 (ε = 0.100%, ε/d = 12.648) [click here to expand/hide] [link to here]


V7: V1:SDB2_B5_QD2_112MHz_V_0 (ε = 0.100%, ε/d = 13.828) [click here to expand/hide] [link to here]


V8: V1:SDB2_B5_QD2_112MHz_H_norm_0 (ε = 0.086%, ε/d = 14.167) [click here to expand/hide] [link to here]


V9: V1:SDB2_B5_QD2_56MHz_H_Q_0 (ε = 0.074%, ε/d = 12.309) [click here to expand/hide] [link to here]


V10: V1:SDB2_B5_QD2_56MHz_V_Q_0 (ε = 0.066%, ε/d = 14.977) [click here to expand/hide] [link to here]


V11: V1:SDB2_B5_QD2_6MHz_V_I_0 (ε = 0.063%, ε/d = 15.404) [click here to expand/hide] [link to here]


V12: V1:SDB2_B5_QD2_6MHz_SUM_I_0 (ε = 0.060%, ε/d = 13.397) [click here to expand/hide] [link to here]


V13: V1:SDB2_B5_QD2_50MHz_SUM_Q_0 (ε = 0.040%, ε/d = 39.531) [click here to expand/hide] [link to here]


V14: V1:SDB2_B5_QD2_50MHz_H_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V15: V1:SDB2_B5_QD2_50MHz_SUM_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V16: V1:SDB2_B5_QD2_50MHz_V_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V17: V1:SDB2_B5_QD2_50MHz_V_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V18: V1:SDB2_B5_QD2_56MHz_H_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V19: V1:SDB2_B5_QD2_56MHz_SUM_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V20: V1:SDB2_B5_QD2_56MHz_SUM_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V21: V1:SDB2_B5_QD2_56MHz_V_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V22: V1:SDB2_B5_QD2_6MHz_H_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V23: V1:SDB2_B5_QD2_6MHz_H_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V24: V1:SDB2_B5_QD2_6MHz_V_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V25: V1:SDB2_B5_QD2_GALVO_H_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V26: V1:SDB2_B5_QD2_GALVO_H_CORR_notsafe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V27: V1:SDB2_B5_QD2_GALVO_V_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V28: V1:SDB2_B5_QD2_GALVO_V_CORR_notsafe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V29: V1:SDB2_B5_QD2_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V30: V1:SDB2_B5_QD2_H_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V31: V1:SDB2_B5_QD2_Sum_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V32: V1:SDB2_B5_QD2_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V33: V1:SDB2_B5_QD2_V_norm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V34: V1:SDB2_CAL_B1p_PD1_DC_10kHz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V35: V1:SDB2_CAL_B1p_PD2_Audio_10kHz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V36: V1:SDB2_CAL_B1p_PD2_Blended_10kHz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V37: V1:SDB2_CAL_B1p_PD2_DC_10kHz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:SDB2_Clock_100MHz_mag_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:SDB2_Clock_100MHz_phi_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:SDB2_GALVO_gene_sum_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:SDB2_LC_COIL_BL_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:SDB2_LC_COIL_BL_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:SDB2_LC_COIL_BR_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:SDB2_LC_COIL_BR_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:SDB2_LC_COIL_FL_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:SDB2_LC_COIL_FL_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:SDB2_LC_COIL_FR_H_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:SDB2_LC_COIL_FR_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:SDB2_LC_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:SDB2_LC_LVDT_BL_H_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:SDB2_LC_LVDT_BL_V_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:SDB2_LC_LVDT_BR_H_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:SDB2_LC_LVDT_BR_V_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:SDB2_LC_LVDT_FL_H_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:SDB2_LC_LVDT_FL_V_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:SDB2_LC_LVDT_FR_H_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:SDB2_LC_LVDT_FR_V_out_raw_1000Hz_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:SDB2_LC_NOISE_flt_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:SDB2_LC_TX_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:SDB2_LC_TX_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:SDB2_LC_TX_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:SDB2_LC_TY_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:SDB2_LC_TY_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:SDB2_LC_TY_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:SDB2_LC_TZ_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:SDB2_LC_TZ_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:SDB2_LC_TZ_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:SDB2_LC_X_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:SDB2_LC_X_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:SDB2_LC_X_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:SDB2_LC_Y_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:SDB2_LC_Y_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:SDB2_LC_Y_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:SDB2_LC_Z_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:SDB2_LC_Z_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:SDB2_LC_Z_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:SDB2_LC_Z_err_ground_corrected_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:SDB2_LC_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:SDB2_POWERSUPPLY_DBOX_LEFT_DOWN_m12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:SDB2_POWERSUPPLY_DBOX_LEFT_UP_m12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:SDB2_POWERSUPPLY_DBOX_LEFT_UP_p12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:SDB2_POWERSUPPLY_DBOX_RIGHT_DOWN_m12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:SDB2_POWERSUPPLY_DBOX_RIGHT_DOWN_p12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:SDB2_POWERSUPPLY_DBOX_RIGHT_UP_m12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:SDB2_POWERSUPPLY_DBOX_RIGHT_UP_p12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:SDB2_POWERSUPPLY_QUADRANT_m18V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:SDB2_POWERSUPPLY_QUADRANT_p18V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:SDB2_POWERSUPPLY_QUADRANT_p24V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:SDB2_POWERSUPPLY_SWITCH_p12V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:SDB2_Photodiodes_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:SDB2_Photodiodes_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:SDB2_Quadrants_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:SDB2_Quadrants_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:SDB2_Readout_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:SDB2_Readout_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:SDB2_SBE_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:SDB2_SBE_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:SDB2_Tpro_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:SDB2_Tpro_processed_packets_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr