VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:0 h, 57 min, 37 s
Processing Date:Fri Jun 20 18:07:22 2025 (UTC)
Requested start:1433251331 → Fri Jun 6 13:21:53 2025 (UTC)
Requested stop:1433662376 → Wed Jun 11 07:32:38 2025 (UTC)
Requested livetime:256511 sec → 2.969 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:48226537
Number of raw clusters:34915
Number of active clusters:34915 (SNR > 5.000) 6124 (SNR > 8.000) 5110 (SNR > 10.000) 3304 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (256511 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 34915 clusters
V0 → V1:LSC_WE_CORR_0, vetoed clusters: 4492 (12.866 %)
V1 → V1:LSC_WI_CORR_0, vetoed clusters: 4488 (12.854 %)
V2 → V1:LSC_PRCL_CORR_0, vetoed clusters: 28 (0.080 %)
V3 → V1:LSC_PRCL_CORR_raw_0, vetoed clusters: 28 (0.080 %)
V4 → V1:LSC_PRCL_0, vetoed clusters: 26 (0.074 %)
V5 → V1:LSC_PRCL_ERR_0, vetoed clusters: 26 (0.074 %)
V6 → V1:LSC_PRCL_INPUT_0, vetoed clusters: 26 (0.074 %)
V7 → V1:LSC_PRCL_DARM_flt_0, vetoed clusters: 26 (0.074 %)
V8 → V1:LSC_SRCL_CORR_0, vetoed clusters: 24 (0.069 %)
V9 → V1:LSC_SRCL_0, vetoed clusters: 23 (0.066 %)

V0: V1:LSC_WE_CORR_0 (ε = 12.866%, ε/d = 147.164) [click here to expand/hide] [link to here]


V1: V1:LSC_WI_CORR_0 (ε = 12.854%, ε/d = 147.001) [click here to expand/hide] [link to here]


V2: V1:LSC_PRCL_CORR_0 (ε = 0.080%, ε/d = 43.068) [click here to expand/hide] [link to here]


V3: V1:LSC_PRCL_CORR_raw_0 (ε = 0.080%, ε/d = 43.068) [click here to expand/hide] [link to here]


V4: V1:LSC_PRCL_0 (ε = 0.074%, ε/d = 41.008) [click here to expand/hide] [link to here]


V5: V1:LSC_PRCL_ERR_0 (ε = 0.074%, ε/d = 41.008) [click here to expand/hide] [link to here]


V6: V1:LSC_PRCL_INPUT_0 (ε = 0.074%, ε/d = 41.008) [click here to expand/hide] [link to here]


V7: V1:LSC_PRCL_DARM_flt_0 (ε = 0.074%, ε/d = 40.146) [click here to expand/hide] [link to here]


V8: V1:LSC_SRCL_CORR_0 (ε = 0.069%, ε/d = 15.744) [click here to expand/hide] [link to here]


V9: V1:LSC_SRCL_0 (ε = 0.066%, ε/d = 15.198) [click here to expand/hide] [link to here]


V10: V1:LSC_SR_CORR_0 (ε = 0.060%, ε/d = 17.641) [click here to expand/hide] [link to here]


V11: V1:LSC_SRCL_ERR_0 (ε = 0.057%, ε/d = 14.031) [click here to expand/hide] [link to here]


V12: V1:LSC_SRCL_INPUT_0 (ε = 0.057%, ε/d = 14.031) [click here to expand/hide] [link to here]


V13: V1:LSC_PR_CORR_0 (ε = 0.054%, ε/d = 51.630) [click here to expand/hide] [link to here]


V14: V1:LSC_PRCL_DARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V15: V1:LSC_PRCL_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V16: V1:LSC_PRCL_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V17: V1:LSC_PRCL_TRIGGER_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V18: V1:LSC_PRCL_TRIGGER_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V19: V1:LSC_PR_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V20: V1:LSC_SRCL_DARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V21: V1:LSC_SRCL_DARM_flt_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V22: V1:LSC_SRCL_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V23: V1:LSC_SRCL_SET_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V24: V1:LSC_SRCL_SET_CORR_CLIP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V25: V1:LSC_SRCL_SET_CORR_FLT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V26: V1:LSC_SRCL_SET_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V27: V1:LSC_SRCL_SET_EN_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V28: V1:LSC_SRCL_SET_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V29: V1:LSC_SRCL_SET_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V30: V1:LSC_SRCL_SET_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V31: V1:LSC_SRCL_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V32: V1:LSC_SRCL_TRIGGER_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V33: V1:LSC_SRCL_TRIGGER_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V34: V1:LSC_SR_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V35: V1:LSC_SUSP_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V36: V1:LSC_SUSP_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V37: V1:LSC_SWITCH_MC_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:LSC_SWITCH_SSFS_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:LSC_WArm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:LSC_WArm_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:LSC_WArm_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:LSC_WArm_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:LSC_WArm_LOCK_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:LSC_WArm_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:LSC_WArm_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:LSC_WE_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:LSC_WE_VIOLIN1_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:LSC_WE_VIOLIN2_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:LSC_WE_VIOLIN3_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:LSC_WE_VIOLIN4_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:LSC_WE_VIOLIN5_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:LSC_WE_VIOLIN6_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:LSC_WE_VIOLIN7_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:LSC_WE_VIOLIN8_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:LSC_WE_VIOLIN_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:LSC_WI_HB_moni_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:LSC_WI_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:LSC_WI_VIOLIN1_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:LSC_WI_VIOLIN2_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:LSC_WI_VIOLIN3_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:LSC_WI_VIOLIN4_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:LSC_WI_VIOLIN5_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:LSC_WI_VIOLIN6_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:LSC_WI_VIOLIN7_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:LSC_WI_VIOLIN8_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:LSC_WI_VIOLIN_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:NCal_NEF_pos_Lateral_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:NCal_NEF_pos_Vertical_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:NCal_NEM_pos_Axial_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:NCal_NEM_pos_Vertical_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:NCal_NEN_box_T_Volts_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:NCal_NEN_motor_T_Volts_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:NCal_NEN_pos_Lateral_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:NCal_NEN_pos_Vertical_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:NCal_NE_hInj_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:NCal_NE_mag_geneE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:NCal_NE_mag_geneS_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:NCal_NNF_box_T_Volts_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:NCal_NNF_motor_T_Volts_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:NCal_NNF_motor_cmd_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:NCal_NNF_motor_cmd_V_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:NCal_NNF_motor_enbl_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:NCal_NNF_motor_enbl_safe_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:NCal_NNF_pos_Axial_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:NCal_NNF_pos_Lateral_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:NCal_NNF_pos_Vertical_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:NCal_NNF_rotor_freq_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:NCal_NNF_rotor_freq_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:NCal_NNF_rotor_freq_enable_boost_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:NCal_NNF_rotor_freq_enable_loop_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:NCal_NNF_rotor_freq_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:NCal_NNF_rotor_phase_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:NCal_NNF_rotor_phase_corr_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:NCal_NNF_rotor_phase_enable_loop_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:NCal_NNF_rotor_phase_err_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:NCal_NNN_box_T_Volts_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:NCal_NNN_microphone_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:NCal_NNN_motor_T_Volts_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:NCal_NNN_motor_cmd_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr