OUTPUT DIRECTORY ./report OUTPUT VERBOSITY 1 TARGET OMICRON V1:Hrec_hoft_16384Hz TARGET CLUSTERDT 0.1 TARGET SNRMIN 7 COINC TIMEWIN 1.0 VETO UPMIN 0.4 VETO UMIN 10 VETO PRINT 0 VETO PERF 5 8 10 20 VETO PERFPRINT 1 0 SOURCE CLUSTERDT 0.1 SOURCE OMICRON V1:LSC_B1_DC SOURCE OMICRON V1:LSC_B1_DC_IN1 SOURCE OMICRON V1:LSC_B1_DC_IN2 SOURCE OMICRON V1:LSC_B1_DC_INPUT SOURCE OMICRON V1:LSC_BS_CORR SOURCE OMICRON V1:LSC_BS_LOCK_FLAG SOURCE OMICRON V1:LSC_CARM SOURCE OMICRON V1:LSC_CARM_CORR SOURCE OMICRON V1:LSC_CARM_DARM_CORR SOURCE OMICRON V1:LSC_CARM_DARM_ON SOURCE OMICRON V1:LSC_CARM_DARM_flt SOURCE OMICRON V1:LSC_CARM_ERR SOURCE OMICRON V1:LSC_CARM_FAST_CORR SOURCE OMICRON V1:LSC_CARM_INPUT SOURCE OMICRON V1:LSC_CARM_MC_ERR SOURCE OMICRON V1:LSC_CARM_MC_INPUT SOURCE OMICRON V1:LSC_CARM_NOISE SOURCE OMICRON V1:LSC_CARM_SLOW SOURCE OMICRON V1:LSC_CARM_SLOW_CORR SOURCE OMICRON V1:LSC_CARM_SLOW_ERR SOURCE OMICRON V1:LSC_CARM_SLOW_TRIG SOURCE OMICRON V1:LSC_CARM_TRIG SOURCE OMICRON V1:LSC_DARM SOURCE OMICRON V1:LSC_DARM_CORR SOURCE OMICRON V1:LSC_DARM_CORR_raw SOURCE OMICRON V1:LSC_DARM_ERR SOURCE OMICRON V1:LSC_DARM_INPUT SOURCE OMICRON V1:LSC_DARM_NOISE SOURCE OMICRON V1:LSC_DARM_TRIG SOURCE OMICRON V1:LSC_DCP_DARM_CORR_FLT_HF SOURCE OMICRON V1:LSC_DCP_DARM_CORR_FLT_LF SOURCE OMICRON V1:LSC_DCP_DARM_ERR_FLT_HF SOURCE OMICRON V1:LSC_DCP_DARM_ERR_FLT_HF_DEL SOURCE OMICRON V1:LSC_DCP_DARM_ERR_FLT_LF SOURCE OMICRON V1:LSC_DCP_DARM_ERR_FLT_LF_DEL SOURCE OMICRON V1:LSC_DCP_MM_IM SOURCE OMICRON V1:LSC_DCP_MM_RE SOURCE OMICRON V1:LSC_DCP_NORM SOURCE OMICRON V1:LSC_DRMI_TRIGGER_IN SOURCE OMICRON V1:LSC_DRMI_TRIGGER_IN1 SOURCE OMICRON V1:LSC_DRMI_TRIGGER_IN2 SOURCE OMICRON V1:LSC_DRMI_TRIGGER_IN3 SOURCE OMICRON V1:LSC_DRMI_TRIGGER_IN4 SOURCE OMICRON V1:LSC_DRMI_TRIGGER_IN4_p SOURCE OMICRON V1:LSC_ENABLE SOURCE OMICRON V1:LSC_Etalon_Acl_elapsed_time SOURCE OMICRON V1:LSC_GREEN_LOCK SOURCE OMICRON V1:LSC_GREEN_LOCK_CHECK SOURCE OMICRON V1:LSC_GREEN_OFF SOURCE OMICRON V1:LSC_LSC_ARMS_ON SOURCE OMICRON V1:LSC_MICH SOURCE OMICRON V1:LSC_MICH_CORR SOURCE OMICRON V1:LSC_MICH_DARM_CORR SOURCE OMICRON V1:LSC_MICH_DARM_flt SOURCE OMICRON V1:LSC_MICH_ERR SOURCE OMICRON V1:LSC_MICH_FILTER_ENBL SOURCE OMICRON V1:LSC_MICH_INPUT SOURCE OMICRON V1:LSC_MICH_NOISE SOURCE OMICRON V1:LSC_MICH_SET_CORR SOURCE OMICRON V1:LSC_MICH_SET_CORR_CLIP SOURCE OMICRON V1:LSC_MICH_SET_CORR_FLT SOURCE OMICRON V1:LSC_MICH_SET_ENBL SOURCE OMICRON V1:LSC_MICH_SET_EN_TRIG SOURCE OMICRON V1:LSC_MICH_SET_IN SOURCE OMICRON V1:LSC_MICH_SET_INPUT SOURCE OMICRON V1:LSC_MICH_SET_TRIG SOURCE OMICRON V1:LSC_MICH_TRIG SOURCE OMICRON V1:LSC_MICH_TRIGGER SOURCE OMICRON V1:LSC_MICH_TRIGGER_INPUT SOURCE OMICRON V1:LSC_NArm SOURCE OMICRON V1:LSC_NArm_CORR SOURCE OMICRON V1:LSC_NArm_ERR SOURCE OMICRON V1:LSC_NArm_INPUT SOURCE OMICRON V1:LSC_NArm_LOCK_ON SOURCE OMICRON V1:LSC_NArm_NOISE SOURCE OMICRON V1:LSC_NArm_TRIG SOURCE OMICRON V1:LSC_NE_CORR SOURCE OMICRON V1:LSC_NE_LOCK_FLAG SOURCE OMICRON V1:LSC_NE_VIOLIN1_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN2_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN3_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN4_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN5_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN6_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN7_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN8_ERR SOURCE OMICRON V1:LSC_NE_VIOLIN_CORR SOURCE OMICRON V1:LSC_NI_CORR SOURCE OMICRON V1:LSC_NI_HB_moni SOURCE OMICRON V1:LSC_NI_LOCK_FLAG SOURCE OMICRON V1:LSC_NI_VIOLIN1_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN2_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN3_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN4_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN5_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN6_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN7_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN8_ERR SOURCE OMICRON V1:LSC_NI_VIOLIN_CORR SOURCE OMICRON V1:LSC_NOISE