VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:1 h, 32 min, 37 s
Processing Date:Fri Jun 20 18:42:22 2025 (UTC)
Requested start:1433251331 → Fri Jun 6 13:21:53 2025 (UTC)
Requested stop:1433662376 → Wed Jun 11 07:32:38 2025 (UTC)
Requested livetime:256511 sec → 2.969 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:48226537
Number of raw clusters:34915
Number of active clusters:34915 (SNR > 5.000) 6124 (SNR > 8.000) 5110 (SNR > 10.000) 3304 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (256511 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 34915 clusters
V0 → V1:LSC_DARM_ERR_0, vetoed clusters: 7413 (21.232 %)
V1 → V1:LSC_B1_DC_0, vetoed clusters: 7359 (21.077 %)
V2 → V1:LSC_B1_DC_IN1_0, vetoed clusters: 7350 (21.051 %)
V3 → V1:LSC_DARM_0, vetoed clusters: 7324 (20.977 %)
V4 → V1:LSC_DARM_INPUT_0, vetoed clusters: 7269 (20.819 %)
V5 → V1:LSC_DARM_CORR_raw_0, vetoed clusters: 7071 (20.252 %)
V6 → V1:LSC_B1_DC_IN2_0, vetoed clusters: 7015 (20.092 %)
V7 → V1:LSC_B1_DC_INPUT_0, vetoed clusters: 7015 (20.092 %)
V8 → V1:LSC_DCP_DARM_CORR_FLT_LF_0, vetoed clusters: 6683 (19.141 %)
V9 → V1:LSC_DCP_DARM_ERR_FLT_HF_0, vetoed clusters: 6442 (18.451 %)

V0: V1:LSC_DARM_ERR_0 (ε = 21.232%, ε/d = 77.615) [click here to expand/hide] [link to here]


V1: V1:LSC_B1_DC_0 (ε = 21.077%, ε/d = 74.647) [click here to expand/hide] [link to here]


V2: V1:LSC_B1_DC_IN1_0 (ε = 21.051%, ε/d = 74.866) [click here to expand/hide] [link to here]


V3: V1:LSC_DARM_0 (ε = 20.977%, ε/d = 74.717) [click here to expand/hide] [link to here]


V4: V1:LSC_DARM_INPUT_0 (ε = 20.819%, ε/d = 75.991) [click here to expand/hide] [link to here]


V5: V1:LSC_DARM_CORR_raw_0 (ε = 20.252%, ε/d = 83.012) [click here to expand/hide] [link to here]


V6: V1:LSC_B1_DC_IN2_0 (ε = 20.092%, ε/d = 80.145) [click here to expand/hide] [link to here]


V7: V1:LSC_B1_DC_INPUT_0 (ε = 20.092%, ε/d = 80.145) [click here to expand/hide] [link to here]


V8: V1:LSC_DCP_DARM_CORR_FLT_LF_0 (ε = 19.141%, ε/d = 82.838) [click here to expand/hide] [link to here]


V9: V1:LSC_DCP_DARM_ERR_FLT_HF_0 (ε = 18.451%, ε/d = 84.256) [click here to expand/hide] [link to here]


V10: V1:LSC_DCP_DARM_ERR_FLT_HF_DEL_0 (ε = 18.158%, ε/d = 83.627) [click here to expand/hide] [link to here]


V11: V1:LSC_DCP_DARM_ERR_FLT_LF_0 (ε = 17.772%, ε/d = 80.723) [click here to expand/hide] [link to here]


V12: V1:LSC_DCP_MM_RE_0 (ε = 17.328%, ε/d = 104.650) [click here to expand/hide] [link to here]


V13: V1:LSC_DCP_DARM_ERR_FLT_LF_DEL_0 (ε = 17.107%, ε/d = 81.690) [click here to expand/hide] [link to here]


V14: V1:LSC_DCP_NORM_0 (ε = 16.600%, ε/d = 80.876) [click here to expand/hide] [link to here]


V15: V1:LSC_DCP_MM_IM_0 (ε = 15.503%, ε/d = 101.748) [click here to expand/hide] [link to here]


V16: V1:LSC_DCP_DARM_CORR_FLT_HF_0 (ε = 14.240%, ε/d = 114.762) [click here to expand/hide] [link to here]


V17: V1:LSC_DARM_CORR_0 (ε = 13.232%, ε/d = 127.573) [click here to expand/hide] [link to here]


V18: V1:LSC_NI_CORR_0 (ε = 12.668%, ε/d = 140.801) [click here to expand/hide] [link to here]


V19: V1:LSC_NE_CORR_0 (ε = 12.582%, ε/d = 142.442) [click here to expand/hide] [link to here]


V20: V1:LSC_CARM_DARM_CORR_0 (ε = 0.347%, ε/d = 17.723) [click here to expand/hide] [link to here]


V21: V1:LSC_CARM_DARM_flt_0 (ε = 0.329%, ε/d = 18.245) [click here to expand/hide] [link to here]


V22: V1:LSC_MICH_SET_INPUT_0 (ε = 0.261%, ε/d = 52.659) [click here to expand/hide] [link to here]


V23: V1:LSC_MICH_SET_CORR_0 (ε = 0.206%, ε/d = 41.770) [click here to expand/hide] [link to here]


V24: V1:LSC_MICH_SET_IN_0 (ε = 0.206%, ε/d = 41.770) [click here to expand/hide] [link to here]


V25: V1:LSC_CARM_0 (ε = 0.135%, ε/d = 8.121) [click here to expand/hide] [link to here]


V26: V1:LSC_CARM_ERR_0 (ε = 0.135%, ε/d = 8.121) [click here to expand/hide] [link to here]


V27: V1:LSC_CARM_INPUT_0 (ε = 0.117%, ε/d = 8.843) [click here to expand/hide] [link to here]


V28: V1:LSC_CARM_SLOW_0 (ε = 0.117%, ε/d = 8.843) [click here to expand/hide] [link to here]


V29: V1:LSC_CARM_SLOW_ERR_0 (ε = 0.117%, ε/d = 8.843) [click here to expand/hide] [link to here]


V30: V1:LSC_BS_CORR_0 (ε = 0.046%, ε/d = 15.600) [click here to expand/hide] [link to here]


V31: V1:LSC_MICH_CORR_0 (ε = 0.046%, ε/d = 15.600) [click here to expand/hide] [link to here]


V32: V1:LSC_MICH_0 (ε = 0.040%, ε/d = 13.770) [click here to expand/hide] [link to here]


V33: V1:LSC_MICH_DARM_CORR_0 (ε = 0.034%, ε/d = 15.160) [click here to expand/hide] [link to here]


V34: V1:LSC_MICH_DARM_flt_0 (ε = 0.034%, ε/d = 15.160) [click here to expand/hide] [link to here]


V35: V1:LSC_MICH_ERR_0 (ε = 0.034%, ε/d = 11.938) [click here to expand/hide] [link to here]


V36: V1:LSC_MICH_INPUT_0 (ε = 0.034%, ε/d = 11.938) [click here to expand/hide] [link to here]


V37: V1:LSC_BS_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:LSC_CARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:LSC_CARM_DARM_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:LSC_CARM_FAST_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:LSC_CARM_MC_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:LSC_CARM_MC_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:LSC_CARM_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:LSC_CARM_SLOW_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:LSC_CARM_SLOW_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:LSC_CARM_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:LSC_DARM_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:LSC_DARM_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:LSC_DRMI_TRIGGER_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:LSC_DRMI_TRIGGER_IN1_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:LSC_DRMI_TRIGGER_IN2_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:LSC_DRMI_TRIGGER_IN3_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:LSC_DRMI_TRIGGER_IN4_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:LSC_DRMI_TRIGGER_IN4_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:LSC_ENABLE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:LSC_Etalon_Acl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:LSC_GREEN_LOCK_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:LSC_GREEN_LOCK_CHECK_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:LSC_GREEN_OFF_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:LSC_LSC_ARMS_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:LSC_MICH_FILTER_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:LSC_MICH_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:LSC_MICH_SET_CORR_CLIP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:LSC_MICH_SET_CORR_FLT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:LSC_MICH_SET_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:LSC_MICH_SET_EN_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:LSC_MICH_SET_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:LSC_MICH_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:LSC_MICH_TRIGGER_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:LSC_MICH_TRIGGER_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:LSC_NArm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:LSC_NArm_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:LSC_NArm_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:LSC_NArm_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:LSC_NArm_LOCK_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:LSC_NArm_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:LSC_NArm_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:LSC_NE_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:LSC_NE_VIOLIN1_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:LSC_NE_VIOLIN2_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:LSC_NE_VIOLIN3_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:LSC_NE_VIOLIN4_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:LSC_NE_VIOLIN5_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:LSC_NE_VIOLIN6_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:LSC_NE_VIOLIN7_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:LSC_NE_VIOLIN8_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:LSC_NE_VIOLIN_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:LSC_NI_HB_moni_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:LSC_NI_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:LSC_NI_VIOLIN1_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:LSC_NI_VIOLIN2_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:LSC_NI_VIOLIN3_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:LSC_NI_VIOLIN4_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:LSC_NI_VIOLIN5_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:LSC_NI_VIOLIN6_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:LSC_NI_VIOLIN7_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:LSC_NI_VIOLIN8_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:LSC_NI_VIOLIN_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:LSC_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr