OUTPUT  DIRECTORY  ./report
OUTPUT  VERBOSITY  1

TARGET  OMICRON    V1:Hrec_hoft_16384Hz
TARGET  CLUSTERDT  0.1
TARGET  SNRMIN     7

COINC   TIMEWIN    1.0

VETO    UPMIN      0.4
VETO    UMIN       10
VETO    PRINT      0
VETO    PERF       5  8  10  20
VETO    PERFPRINT  1  0

SOURCE  CLUSTERDT  0.1
SOURCE  OMICRON    V1:Sc_MC_MIR_TX
SOURCE  OMICRON    V1:Sc_MC_MIR_TX_CORR
SOURCE  OMICRON    V1:Sc_MC_MIR_TY
SOURCE  OMICRON    V1:Sc_MC_MIR_TY_CORR
SOURCE  OMICRON    V1:Sc_MC_MIR_VOUT_D
SOURCE  OMICRON    V1:Sc_MC_MIR_VOUT_L
SOURCE  OMICRON    V1:Sc_MC_MIR_VOUT_R
SOURCE  OMICRON    V1:Sc_MC_MIR_VOUT_U
SOURCE  OMICRON    V1:Sc_MC_MIR_Z
SOURCE  OMICRON    V1:Sc_MC_MIR_Z_CORR
SOURCE  OMICRON    V1:Sc_MC_RFC_Err_Post
SOURCE  OMICRON    V1:Sc_MC_RFC_Err_Pre
SOURCE  OMICRON    V1:Sc_MC_RFC_On
SOURCE  OMICRON    V1:Sc_MC_RM_MIR_TY
SOURCE  OMICRON    V1:Sc_MC_RM_TY
SOURCE  OMICRON    V1:Sc_MC_RM_TZ
SOURCE  OMICRON    V1:Sc_MC_SSFS_ON
SOURCE  OMICRON    V1:Sc_MC_noise
SOURCE  OMICRON    V1:Sc_MC_txE_p
SOURCE  OMICRON    V1:Sc_NE_ErrPost
SOURCE  OMICRON    V1:Sc_NE_F7_LVDT_H1
SOURCE  OMICRON    V1:Sc_NE_F7_LVDT_H2
SOURCE  OMICRON    V1:Sc_NE_F7_LVDT_H3
SOURCE  OMICRON    V1:Sc_NE_F7_LVDT_V1
SOURCE  OMICRON    V1:Sc_NE_F7_LVDT_V2
SOURCE  OMICRON    V1:Sc_NE_F7_LVDT_V3
SOURCE  OMICRON    V1:Sc_NE_F7_TX
SOURCE  OMICRON    V1:Sc_NE_F7_TX_CORR
SOURCE  OMICRON    V1:Sc_NE_F7_TY
SOURCE  OMICRON    V1:Sc_NE_F7_TY_CORR
SOURCE  OMICRON    V1:Sc_NE_F7_TZ
SOURCE  OMICRON    V1:Sc_NE_F7_TZ_CORR
SOURCE  OMICRON    V1:Sc_NE_F7_X
SOURCE  OMICRON    V1:Sc_NE_F7_Y
SOURCE  OMICRON    V1:Sc_NE_F7_Z
SOURCE  OMICRON    V1:Sc_NE_F7_Z_CORR
SOURCE  OMICRON    V1:Sc_NE_MAR_COIL_FLAG
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDM_PWR
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDM_X1
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDM_X2
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDM_Y1
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDM_Y2
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDT_PWR
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDT_X1
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDT_Y1
SOURCE  OMICRON    V1:Sc_NE_MAR_PSDT_Y2
SOURCE  OMICRON    V1:Sc_NE_MAR_TX
SOURCE  OMICRON    V1:Sc_NE_MAR_TX_CORR
SOURCE  OMICRON    V1:Sc_NE_MAR_TY
SOURCE  OMICRON    V1:Sc_NE_MAR_TY_CORR
SOURCE  OMICRON    V1:Sc_NE_MAR_TY_T
SOURCE  OMICRON    V1:Sc_NE_MAR_TZ
SOURCE  OMICRON    V1:Sc_NE_MAR_TZ_CORR
SOURCE  OMICRON    V1:Sc_NE_MAR_Y_CORR
SOURCE  OMICRON    V1:Sc_NE_MIR_COIL_FLAG
SOURCE  OMICRON    V1:Sc_NE_MIR_LSC_CORR
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDF_PWR
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDF_X1
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDF_X2
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDF_Y1
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDF_Y2
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDI_PWR
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDI_X2
SOURCE  OMICRON    V1:Sc_NE_MIR_PSDI_Y2
SOURCE  OMICRON    V1:Sc_NE_MIR_TX
SOURCE  OMICRON    V1:Sc_NE_MIR_TY
SOURCE  OMICRON    V1:Sc_NE_MIR_VOUT_DL
SOURCE  OMICRON    V1:Sc_NE_MIR_VOUT_DR
SOURCE  OMICRON    V1:Sc_NE_MIR_VOUT_UL
SOURCE  OMICRON    V1:Sc_NE_MIR_VOUT_UR
SOURCE  OMICRON    V1:Sc_NE_MIR_X_AA
SOURCE  OMICRON    V1:Sc_NE_MIR_Y_AA
SOURCE  OMICRON    V1:Sc_NE_MIR_Z
SOURCE  OMICRON    V1:Sc_NE_MIR_Z_CORR
SOURCE  OMICRON    V1:Sc_NE_MIR_Z_CORR_LN
SOURCE  OMICRON    V1:Sc_NE_NA_Ctx
SOURCE  OMICRON    V1:Sc_NE_NA_Cty
SOURCE  OMICRON    V1:Sc_NE_noise
SOURCE  OMICRON    V1:Sc_NE_txAA
SOURCE  OMICRON    V1:Sc_NE_tyAA
SOURCE  OMICRON    V1:Sc_NI_F7_COIL_H1
SOURCE  OMICRON    V1:Sc_NI_F7_COIL_H2
SOURCE  OMICRON    V1:Sc_NI_F7_COIL_H3
SOURCE  OMICRON    V1:Sc_NI_F7_COIL_V1
SOURCE  OMICRON    V1:Sc_NI_F7_COIL_V2
SOURCE  OMICRON    V1:Sc_NI_F7_COIL_V3
SOURCE  OMICRON    V1:Sc_NI_F7_LVDT_H1
SOURCE  OMICRON    V1:Sc_NI_F7_LVDT_H2
SOURCE  OMICRON    V1:Sc_NI_F7_LVDT_H3
SOURCE  OMICRON    V1:Sc_NI_F7_LVDT_V1
SOURCE  OMICRON    V1:Sc_NI_F7_LVDT_V2
SOURCE  OMICRON    V1:Sc_NI_F7_LVDT_V3
SOURCE  OMICRON    V1:Sc_NI_F7_TX
SOURCE  OMICRON    V1:Sc_NI_F7_TX_CORR
SOURCE  OMICRON    V1:Sc_NI_F7_TY
SOURCE  OMICRON    V1:Sc_NI_F7_TY_CORR
SOURCE  OMICRON    V1:Sc_NI_F7_TZ
SOURCE  OMICRON    V1:Sc_NI_F7_TZ_CORR
SOURCE  OMICRON    V1:Sc_NI_F7_X
SOURCE  OMICRON    V1:Sc_NI_F7_Y