UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:0 h, 13 min, 1 s
Processing Date:Thu Feb 13 10:02:02 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:825629 sec → 9.556 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (166): V1:SPRB_B4_PD2_Audio_0 [click here to expand/hide] [link to here]


V1 (165): V1:SPRB_B4_PD2_Blended_0 [click here to expand/hide] [link to here]


V2 (164): V1:SPRB_B4_PD2_Blended_D_0 [click here to expand/hide] [link to here]


V3 (127): V1:SPRB_B4_QD1_12MHz_Sum_0 [click here to expand/hide] [link to here]


V4 (120): V1:SPRB_B4_QD2_12MHz_Sum_0 [click here to expand/hide] [link to here]


V5 (102): V1:SPRB_B4_QD1_50MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V6 (93): V1:SPRB_B4_QD2_50MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V7 (84): V1:SPRB_B4_QD2_6MHz_H_I_0 [click here to expand/hide] [link to here]


V8 (79): V1:SPRB_B4_QD2_56MHz_H_I_0 [click here to expand/hide] [link to here]


V9 (79): V1:SPRB_B4_PD2_DC_0 [click here to expand/hide] [link to here]


V10 (70): V1:SPRB_B4_QD1_Sum_0 [click here to expand/hide] [link to here]


V11 (61): V1:SPRB_B4_QD2_Sum_0 [click here to expand/hide] [link to here]


V12 (51): V1:SPRB_B4_QD2_56MHz_SUM_I_0 [click here to expand/hide] [link to here]


V13 (49): V1:SPRB_B4_QD1_56MHz_SUM_I_0 [click here to expand/hide] [link to here]


V14 (48): V1:SPRB_B4_QD1_6MHz_H_I_0 [click here to expand/hide] [link to here]


V15 (43): V1:SPRB_B4_QD1_6MHz_V_I_0 [click here to expand/hide] [link to here]


V16 (40): V1:SPRB_B4_QD1_50MHz_SUM_I_0 [click here to expand/hide] [link to here]


V17 (39): V1:SPRB_B4_QD1_56MHz_V_Q_0 [click here to expand/hide] [link to here]


V18 (37): V1:SPRB_B4_QD2_50MHz_SUM_I_0 [click here to expand/hide] [link to here]


V19 (35): V1:SPRB_B4_QD2_6MHz_V_Q_0 [click here to expand/hide] [link to here]


V20 (35): V1:SPRB_B4_QD2_6MHz_V_I_0 [click here to expand/hide] [link to here]


V21 (35): V1:SPRB_B4_QD2_56MHz_V_I_0 [click here to expand/hide] [link to here]


V22 (34): V1:SPRB_B4_QD2_H_0 [click here to expand/hide] [link to here]


V23 (33): V1:SPRB_B4_QD2_6MHz_SUM_I_0 [click here to expand/hide] [link to here]


V24 (33): V1:SPRB_B4_QD1_50MHz_H_I_0 [click here to expand/hide] [link to here]


V25 (32): V1:SPRB_B4_QD2_H_norm_0 [click here to expand/hide] [link to here]


V26 (32): V1:SPRB_B4_QD2_6MHz_H_Q_0 [click here to expand/hide] [link to here]


V27 (32): V1:SPRB_B4_QD1_56MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V28 (31): V1:SPRB_B4_QD2_6MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V29 (31): V1:SPRB_B4_QD1_6MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V30 (31): V1:SPRB_B4_QD1_112MHz_Sum_0 [click here to expand/hide] [link to here]


V31 (29): V1:SPRB_B4_QD1_56MHz_H_I_0 [click here to expand/hide] [link to here]


V32 (27): V1:SPRB_B4_QD2_V_norm_0 [click here to expand/hide] [link to here]


V33 (26): V1:SPRB_B4_QD1_H_norm_0 [click here to expand/hide] [link to here]


V34 (26): V1:SPRB_B4_QD1_56MHz_H_Q_0 [click here to expand/hide] [link to here]


V35 (25): V1:SPRB_B4_QD1_6MHz_V_Q_0 [click here to expand/hide] [link to here]


V36 (24): V1:SPRB_B4_QD2_112MHz_Sum_0 [click here to expand/hide] [link to here]


V37 (24): V1:SPRB_B4_QD1_56MHz_V_I_0 [click here to expand/hide] [link to here]


V38 (24): V1:SPRB_B4_QD1_50MHz_H_Q_0 [click here to expand/hide] [link to here]


V39 (23): V1:SPRB_B4_QD2_56MHz_H_Q_0 [click here to expand/hide] [link to here]


V40 (21): V1:SPRB_B4_QD1_H_0 [click here to expand/hide] [link to here]


V41 (16): V1:SPRB_B4_QD2_V_0 [click here to expand/hide] [link to here]


V42 (13): V1:SPRB_B4_QD2_56MHz_V_Q_0 [click here to expand/hide] [link to here]


V43 (13): V1:SPRB_B4_QD2_50MHz_H_I_0 [click here to expand/hide] [link to here]


V44 (12): V1:SPRB_B4_QD1_GALVO_V_CORR_notsafe_0 [click here to expand/hide] [link to here]


V45 (12): V1:SPRB_B4_QD1_GALVO_V_CORR_0 [click here to expand/hide] [link to here]


V46 (12): V1:SPRB_B4_QD1_50MHz_V_Q_0 [click here to expand/hide] [link to here]


V47 (0): V1:SPRB_LC_LVDT_BR_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V48 (0): V1:SPRB_LC_LVDT_BL_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V49 (0): V1:SPRB_LC_LVDT_BL_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V50 (0): V1:SPRB_LC_CfgChange_0 [click here to expand/hide] [link to here]


V51 (0): V1:SPRB_LC_COIL_FR_V_0 [click here to expand/hide] [link to here]


V52 (0): V1:SPRB_LC_COIL_FR_H_0 [click here to expand/hide] [link to here]


V53 (0): V1:SPRB_LC_COIL_FL_V_0 [click here to expand/hide] [link to here]


V54 (0): V1:SPRB_LC_COIL_FL_H_0 [click here to expand/hide] [link to here]


V55 (0): V1:SPRB_LC_COIL_BR_V_0 [click here to expand/hide] [link to here]


V56 (0): V1:SPRB_LC_COIL_BR_H_0 [click here to expand/hide] [link to here]


V57 (0): V1:SPRB_LC_COIL_BL_V_0 [click here to expand/hide] [link to here]


V58 (0): V1:SPRB_LC_COIL_BL_H_0 [click here to expand/hide] [link to here]


V59 (0): V1:SPRB_LC_B4_QD2_enbl_safe_0 [click here to expand/hide] [link to here]


V60 (0): V1:SPRB_LC_B4_QD2_enbl_0 [click here to expand/hide] [link to here]


V61 (0): V1:SPRB_LC_B4_QD2_TY_err_0 [click here to expand/hide] [link to here]


V62 (0): V1:SPRB_LC_B4_QD2_TX_err_0 [click here to expand/hide] [link to here]


V63 (0): V1:SPRB_GALVO_gene_sum_0 [click here to expand/hide] [link to here]


V64 (0): V1:SPRB_Clock_100MHz_phi_0 [click here to expand/hide] [link to here]


V65 (0): V1:SPRB_Clock_100MHz_mag_0 [click here to expand/hide] [link to here]


V66 (0): V1:SPRB_B4_QD2_GALVO_V_CORR_notsafe_0 [click here to expand/hide] [link to here]


V67 (0): V1:SPRB_B4_QD2_GALVO_V_CORR_0 [click here to expand/hide] [link to here]


V68 (0): V1:SPRB_B4_QD2_GALVO_H_CORR_notsafe_0 [click here to expand/hide] [link to here]


V69 (0): V1:SPRB_B4_QD2_GALVO_H_CORR_0 [click here to expand/hide] [link to here]


V70 (0): V1:SPRB_B4_QD2_56MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V71 (0): V1:SPRB_B4_QD2_50MHz_V_Q_0 [click here to expand/hide] [link to here]


V72 (0): V1:SPRB_B4_QD2_50MHz_V_I_0 [click here to expand/hide] [link to here]


V73 (0): V1:SPRB_B4_QD2_50MHz_H_Q_0 [click here to expand/hide] [link to here]


V74 (0): V1:SPRB_B4_QD2_12MHz_V_norm_0 [click here to expand/hide] [link to here]


V75 (0): V1:SPRB_B4_QD2_12MHz_V_0 [click here to expand/hide] [link to here]


V76 (0): V1:SPRB_B4_QD2_12MHz_H_norm_0 [click here to expand/hide] [link to here]


V77 (0): V1:SPRB_B4_QD2_12MHz_H_0 [click here to expand/hide] [link to here]


V78 (0): V1:SPRB_B4_QD2_112MHz_V_norm_0 [click here to expand/hide] [link to here]


V79 (0): V1:SPRB_B4_QD2_112MHz_V_0 [click here to expand/hide] [link to here]


V80 (0): V1:SPRB_B4_QD2_112MHz_H_norm_0 [click here to expand/hide] [link to here]


V81 (0): V1:SPRB_B4_QD2_112MHz_H_0 [click here to expand/hide] [link to here]


V82 (0): V1:SPRB_B4_QD1_V_norm_0 [click here to expand/hide] [link to here]


V83 (0): V1:SPRB_B4_QD1_V_0 [click here to expand/hide] [link to here]


V84 (0): V1:SPRB_B4_QD1_GALVO_H_CORR_notsafe_0 [click here to expand/hide] [link to here]


V85 (0): V1:SPRB_B4_QD1_GALVO_H_CORR_0 [click here to expand/hide] [link to here]


V86 (0): V1:SPRB_B4_QD1_6MHz_SUM_I_0 [click here to expand/hide] [link to here]


V87 (0): V1:SPRB_B4_QD1_6MHz_H_Q_0 [click here to expand/hide] [link to here]


V88 (0): V1:SPRB_B4_QD1_50MHz_V_I_0 [click here to expand/hide] [link to here]


V89 (0): V1:SPRB_B4_QD1_12MHz_V_norm_0 [click here to expand/hide] [link to here]


V90 (0): V1:SPRB_B4_QD1_12MHz_V_0 [click here to expand/hide] [link to here]


V91 (0): V1:SPRB_B4_QD1_12MHz_H_norm_0 [click here to expand/hide] [link to here]


V92 (0): V1:SPRB_B4_QD1_12MHz_H_0 [click here to expand/hide] [link to here]


V93 (0): V1:SPRB_B4_QD1_112MHz_V_norm_0 [click here to expand/hide] [link to here]


V94 (0): V1:SPRB_B4_QD1_112MHz_V_0 [click here to expand/hide] [link to here]


V95 (0): V1:SPRB_B4_QD1_112MHz_H_norm_0 [click here to expand/hide] [link to here]


V96 (0): V1:SPRB_B4_QD1_112MHz_H_0 [click here to expand/hide] [link to here]


V97 (0): V1:SPRB_B4_PD_select_0 [click here to expand/hide] [link to here]


V98 (0): V1:SPRB_B4_PD2_VBias_0 [click here to expand/hide] [link to here]


V99 (0): V1:SPRB_B4_PD2_IBias_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr