Index of /frobinet/upv/1420288240.1421478029/report.32.45924611/V1:Hrec_hoft_16384Hz/
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V1:SPRB_B4_PD2_Audio_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_PD2_Blended_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_PD2_Blended_D_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_PD2_DC_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_PD2_IBias_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_PD2_VBias_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_PD_select_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_112MHz_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_112MHz_H_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_112MHz_Sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_112MHz_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_112MHz_V_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_12MHz_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_12MHz_H_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_12MHz_Sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_12MHz_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_12MHz_V_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_50MHz_H_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_50MHz_H_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_50MHz_SUM_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_50MHz_SUM_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_50MHz_V_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_50MHz_V_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_56MHz_H_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_56MHz_H_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_56MHz_SUM_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_56MHz_SUM_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_56MHz_V_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_56MHz_V_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_6MHz_H_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_6MHz_H_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_6MHz_SUM_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_6MHz_SUM_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_6MHz_V_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_6MHz_V_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_GALVO_H_CORR_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_GALVO_H_CORR_notsafe_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_GALVO_V_CORR_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_GALVO_V_CORR_notsafe_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_H_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_Sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD1_V_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_112MHz_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_112MHz_H_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_112MHz_Sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_112MHz_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_112MHz_V_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_12MHz_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_12MHz_H_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_12MHz_Sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_12MHz_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_12MHz_V_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_50MHz_H_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_50MHz_H_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_50MHz_SUM_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_50MHz_SUM_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_50MHz_V_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_50MHz_V_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_56MHz_H_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_56MHz_H_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_56MHz_SUM_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_56MHz_SUM_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_56MHz_V_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_56MHz_V_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_6MHz_H_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_6MHz_H_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_6MHz_SUM_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_6MHz_SUM_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_6MHz_V_I_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_6MHz_V_Q_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_GALVO_H_CORR_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_GALVO_H_CORR_notsafe_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_GALVO_V_CORR_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_GALVO_V_CORR_notsafe_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_H_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_Sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_B4_QD2_V_norm_0/ 13-Feb-2025 14:25 -
V1:SPRB_Clock_100MHz_mag_0/ 13-Feb-2025 14:25 -
V1:SPRB_Clock_100MHz_phi_0/ 13-Feb-2025 14:25 -
V1:SPRB_GALVO_gene_sum_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_B4_QD2_TX_err_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_B4_QD2_TY_err_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_B4_QD2_enbl_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_B4_QD2_enbl_safe_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_BL_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_BL_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_BR_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_BR_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_FL_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_FL_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_FR_H_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_COIL_FR_V_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_CfgChange_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_LVDT_BL_H_out_raw_1000Hz_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_LVDT_BL_V_out_raw_1000Hz_0/ 13-Feb-2025 14:25 -
V1:SPRB_LC_LVDT_BR_H_out_raw_1000Hz_0/ 13-Feb-2025 14:25 -
perf/ 13-Feb-2025 14:25 -