UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:4 h, 56 min, 0 s
Processing Date:Thu Feb 13 14:45:01 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:825629 sec → 9.556 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (176): V1:BsX_QN_DC_0 [click here to expand/hide] [link to here]


V1 (175): V1:BsX_GLB05_0 [click here to expand/hide] [link to here]


V2 (172): V1:BsX_QN_h_0 [click here to expand/hide] [link to here]


V3 (168): V1:BsX_QF_DC_0 [click here to expand/hide] [link to here]


V4 (124): V1:BsX_QF_h_0 [click here to expand/hide] [link to here]


V5 (117): V1:BsX_QN_v_0 [click here to expand/hide] [link to here]


V6 (103): V1:BsX_QF_v_0 [click here to expand/hide] [link to here]


V7 (55): V1:ASC_PR_TX_OUT_0 [click here to expand/hide] [link to here]


V8 (42): V1:BsX_PZT_DVC_0 [click here to expand/hide] [link to here]


V9 (42): V1:BsX_PZT_DV_0 [click here to expand/hide] [link to here]


V10 (36): V1:BsX_Y_0 [click here to expand/hide] [link to here]


V11 (33): V1:BsX_Y_CORR_0 [click here to expand/hide] [link to here]


V12 (30): V1:BsX_TX_CORR_0 [click here to expand/hide] [link to here]


V13 (29): V1:BsX_PZT_UVC_0 [click here to expand/hide] [link to here]


V14 (29): V1:BsX_PZT_UV_0 [click here to expand/hide] [link to here]


V15 (27): V1:ASC_WE_TY_CORR_0 [click here to expand/hide] [link to here]


V16 (19): V1:ASC_PR_TY_OUT_0 [click here to expand/hide] [link to here]


V17 (19): V1:ASC_PR_TY_IN_0 [click here to expand/hide] [link to here]


V18 (19): V1:ASC_PR_TY_ERR_0 [click here to expand/hide] [link to here]


V19 (19): V1:ASC_PR_TY_0 [click here to expand/hide] [link to here]


V20 (18): V1:BsX_X_0 [click here to expand/hide] [link to here]


V21 (18): V1:BsX_TY_CORR_0 [click here to expand/hide] [link to here]


V22 (18): V1:BsX_PZT_UHC_0 [click here to expand/hide] [link to here]


V23 (18): V1:BsX_PZT_UH_0 [click here to expand/hide] [link to here]


V24 (18): V1:BsX_PZT_DHC_0 [click here to expand/hide] [link to here]


V25 (18): V1:BsX_PZT_DH_0 [click here to expand/hide] [link to here]


V26 (18): V1:ASC_PR_TY_INPUT_0 [click here to expand/hide] [link to here]


V27 (18): V1:ASC_PR_TY_CORR_0 [click here to expand/hide] [link to here]


V28 (17): V1:BsX_Mon_PZ1_0 [click here to expand/hide] [link to here]


V29 (17): V1:BsX_GLB00_0 [click here to expand/hide] [link to here]


V30 (17): V1:ASC_WE_TX_CORR_0 [click here to expand/hide] [link to here]


V31 (15): V1:BsX_TY_0 [click here to expand/hide] [link to here]


V32 (0): V1:BsX_checkPSD_0 [click here to expand/hide] [link to here]


V33 (0): V1:BsX_X_CORR_0 [click here to expand/hide] [link to here]


V34 (0): V1:BsX_TX_0 [click here to expand/hide] [link to here]


V35 (0): V1:BsX_PWRTrig_0 [click here to expand/hide] [link to here]


V36 (0): V1:BsX_ML_TH_CORR_0 [click here to expand/hide] [link to here]


V37 (0): V1:BsX_ML_PZT_CORR_0 [click here to expand/hide] [link to here]


V38 (0): V1:BsX_GLB06_0 [click here to expand/hide] [link to here]


V39 (0): V1:BsX_GLB04_0 [click here to expand/hide] [link to here]


V40 (0): V1:BsX_GLB03_0 [click here to expand/hide] [link to here]


V41 (0): V1:BsX_GLB02_0 [click here to expand/hide] [link to here]


V42 (0): V1:BsX_GLB01_0 [click here to expand/hide] [link to here]


V43 (0): V1:BsX_Driftsw_0 [click here to expand/hide] [link to here]


V44 (0): V1:BsX_AAsw_0 [click here to expand/hide] [link to here]


V45 (0): V1:ASC_pre_elapsed_time_0 [click here to expand/hide] [link to here]


V46 (0): V1:ASC_pre_CfgChange_0 [click here to expand/hide] [link to here]


V47 (0): V1:ASC_WI_TY_ON_0 [click here to expand/hide] [link to here]


V48 (0): V1:ASC_WI_TY_NOISE_0 [click here to expand/hide] [link to here]


V49 (0): V1:ASC_WI_TY_CORR_0 [click here to expand/hide] [link to here]


V50 (0): V1:ASC_WI_TX_ON_0 [click here to expand/hide] [link to here]


V51 (0): V1:ASC_WI_TX_NOISE_0 [click here to expand/hide] [link to here]


V52 (0): V1:ASC_WI_TX_CORR_0 [click here to expand/hide] [link to here]


V53 (0): V1:ASC_WE_TY_ON_0 [click here to expand/hide] [link to here]


V54 (0): V1:ASC_WE_TY_NOISE_0 [click here to expand/hide] [link to here]


V55 (0): V1:ASC_WE_TX_ON_0 [click here to expand/hide] [link to here]


V56 (0): V1:ASC_WE_TX_NOISE_0 [click here to expand/hide] [link to here]


V57 (0): V1:ASC_SR_TY_TRIG_0 [click here to expand/hide] [link to here]


V58 (0): V1:ASC_SR_TY_OUT_0 [click here to expand/hide] [link to here]


V59 (0): V1:ASC_SR_TY_NOISE_0 [click here to expand/hide] [link to here]


V60 (0): V1:ASC_SR_TY_INPUT_0 [click here to expand/hide] [link to here]


V61 (0): V1:ASC_SR_TY_IN_0 [click here to expand/hide] [link to here]


V62 (0): V1:ASC_SR_TY_ERR_0 [click here to expand/hide] [link to here]


V63 (0): V1:ASC_SR_TY_ENBL_0 [click here to expand/hide] [link to here]


V64 (0): V1:ASC_SR_TY_B1p_DCP_0 [click here to expand/hide] [link to here]


V65 (0): V1:ASC_SR_TY_0 [click here to expand/hide] [link to here]


V66 (0): V1:ASC_SR_TX_TRIG_0 [click here to expand/hide] [link to here]


V67 (0): V1:ASC_SR_TX_OUT_0 [click here to expand/hide] [link to here]


V68 (0): V1:ASC_SR_TX_NOISE_0 [click here to expand/hide] [link to here]


V69 (0): V1:ASC_SR_TX_INPUT_0 [click here to expand/hide] [link to here]


V70 (0): V1:ASC_SR_TX_IN_0 [click here to expand/hide] [link to here]


V71 (0): V1:ASC_SR_TX_ERR_0 [click here to expand/hide] [link to here]


V72 (0): V1:ASC_SR_TX_ENBL_0 [click here to expand/hide] [link to here]


V73 (0): V1:ASC_SR_TX_B1p_DCP_0 [click here to expand/hide] [link to here]


V74 (0): V1:ASC_SR_TX_0 [click here to expand/hide] [link to here]


V75 (0): V1:ASC_SR_DOF_TY_CORR_0 [click here to expand/hide] [link to here]


V76 (0): V1:ASC_SR_DOF_TX_CORR_0 [click here to expand/hide] [link to here]


V77 (0): V1:ASC_PR_Y_TRIG_0 [click here to expand/hide] [link to here]


V78 (0): V1:ASC_PR_Y_ON_0 [click here to expand/hide] [link to here]


V79 (0): V1:ASC_PR_Y_NOISE_0 [click here to expand/hide] [link to here]


V80 (0): V1:ASC_PR_Y_INPUT_0 [click here to expand/hide] [link to here]


V81 (0): V1:ASC_PR_Y_IN_0 [click here to expand/hide] [link to here]


V82 (0): V1:ASC_PR_Y_ENBL_0 [click here to expand/hide] [link to here]


V83 (0): V1:ASC_PR_Y_CORR_0 [click here to expand/hide] [link to here]


V84 (0): V1:ASC_PR_Y_0 [click here to expand/hide] [link to here]


V85 (0): V1:ASC_PR_X_TRIG_0 [click here to expand/hide] [link to here]


V86 (0): V1:ASC_PR_X_ON_0 [click here to expand/hide] [link to here]


V87 (0): V1:ASC_PR_X_NOISE_0 [click here to expand/hide] [link to here]


V88 (0): V1:ASC_PR_X_INPUT_0 [click here to expand/hide] [link to here]


V89 (0): V1:ASC_PR_X_IN_0 [click here to expand/hide] [link to here]


V90 (0): V1:ASC_PR_X_ENBL_0 [click here to expand/hide] [link to here]


V91 (0): V1:ASC_PR_X_CORR_0 [click here to expand/hide] [link to here]


V92 (0): V1:ASC_PR_X_0 [click here to expand/hide] [link to here]


V93 (0): V1:ASC_PR_TY_TRIG_0 [click here to expand/hide] [link to here]


V94 (0): V1:ASC_PR_TY_ON_0 [click here to expand/hide] [link to here]


V95 (0): V1:ASC_PR_TY_NOISE_0 [click here to expand/hide] [link to here]


V96 (0): V1:ASC_PR_TY_ENBL_0 [click here to expand/hide] [link to here]


V97 (0): V1:ASC_PR_TY_B4_12MHz_ENBL_0 [click here to expand/hide] [link to here]


V98 (0): V1:ASC_PR_TX_TRIG_0 [click here to expand/hide] [link to here]


V99 (0): V1:ASC_PR_TX_ON_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr