UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:0 h, 12 min, 7 s
Processing Date:Thu Feb 13 10:01:08 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:825629 sec → 9.556 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (185): V1:SIB2_RFC_PD1_Audio_0 [click here to expand/hide] [link to here]


V1 (185): V1:SIB2_B2_QD2_Sum_0 [click here to expand/hide] [link to here]


V2 (178): V1:SIB2_RFC_PD1_DC_0 [click here to expand/hide] [link to here]


V3 (160): V1:SIB2_RFC_PD2_12MHz_mag_0 [click here to expand/hide] [link to here]


V4 (150): V1:SIB2_RFC_PD1_12MHz_mag_0 [click here to expand/hide] [link to here]


V5 (127): V1:SIB2_B2_QD2_V_norm_0 [click here to expand/hide] [link to here]


V6 (123): V1:SIB2_B2_QD2_6MHz_SUM_I_0 [click here to expand/hide] [link to here]


V7 (114): V1:SIB2_B2_QD2_H_0 [click here to expand/hide] [link to here]


V8 (103): V1:SIB2_B2_QD2_6MHz_V_I_0 [click here to expand/hide] [link to here]


V9 (102): V1:SIB2_B2_QD2_56MHz_SUM_I_0 [click here to expand/hide] [link to here]


V10 (101): V1:SIB2_B2_QD2_V_0 [click here to expand/hide] [link to here]


V11 (98): V1:SIB2_RFC_PD2_6MHz_I_0 [click here to expand/hide] [link to here]


V12 (88): V1:SIB2_RFC_PD2_6MHz_Q_0 [click here to expand/hide] [link to here]


V13 (51): V1:SIB2_B2_QD2_56MHz_V_I_0 [click here to expand/hide] [link to here]


V14 (48): V1:SIB2_B2_QD2_56MHz_H_I_0 [click here to expand/hide] [link to here]


V15 (47): V1:SIB2_B2_QD2_56MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V16 (45): V1:SIB2_B2_QD2_8MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V17 (42): V1:SIB2_RFC_PD1_6MHz_I_0 [click here to expand/hide] [link to here]


V18 (42): V1:SIB2_RFC_6MHz_It_0 [click here to expand/hide] [link to here]


V19 (42): V1:SIB2_RFC_6MHz_I_0 [click here to expand/hide] [link to here]


V20 (39): V1:SIB2_B2_QD2_6MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V21 (30): V1:SIB2_B2_QD2_56MHz_H_Q_0 [click here to expand/hide] [link to here]


V22 (29): V1:SIB2_B2_QD2_6MHz_V_Q_0 [click here to expand/hide] [link to here]


V23 (29): V1:SIB2_B2_QD2_6MHz_H_Q_0 [click here to expand/hide] [link to here]


V24 (25): V1:SIB2_RFC_PD1_6MHz_Q_0 [click here to expand/hide] [link to here]


V25 (25): V1:SIB2_RFC_6MHz_Q_0 [click here to expand/hide] [link to here]


V26 (25): V1:SIB2_B2_QD2_56MHz_V_Q_0 [click here to expand/hide] [link to here]


V27 (17): V1:SIB2_B2_QD2_6MHz_H_I_0 [click here to expand/hide] [link to here]


V28 (11): V1:SIB2_RFC_PD1_56MHz_Q_0 [click here to expand/hide] [link to here]


V29 (0): V1:SIB2_RFC_PD2_12MHz_phi_0 [click here to expand/hide] [link to here]


V30 (0): V1:SIB2_RFC_PD1_VBias_0 [click here to expand/hide] [link to here]


V31 (0): V1:SIB2_RFC_PD1_IBias_0 [click here to expand/hide] [link to here]


V32 (0): V1:SIB2_RFC_PD1_8MHz_Q_0 [click here to expand/hide] [link to here]


V33 (0): V1:SIB2_RFC_PD1_8MHz_I_0 [click here to expand/hide] [link to here]


V34 (0): V1:SIB2_RFC_PD1_56MHz_I_0 [click here to expand/hide] [link to here]


V35 (0): V1:SIB2_RFC_PD1_12MHz_phi_0 [click here to expand/hide] [link to here]


V36 (0): V1:SIB2_RFC_8MHz_I_0 [click here to expand/hide] [link to here]


V37 (0): V1:SIB2_Quadrants_elapsed_time_0 [click here to expand/hide] [link to here]


V38 (0): V1:SIB2_Quadrants_CfgChange_0 [click here to expand/hide] [link to here]


V39 (0): V1:SIB2_Photodiodes_elapsed_time_0 [click here to expand/hide] [link to here]


V40 (0): V1:SIB2_Photodiodes_CfgChange_0 [click here to expand/hide] [link to here]


V41 (0): V1:SIB2_LC_elapsed_time_0 [click here to expand/hide] [link to here]


V42 (0): V1:SIB2_LC_Z_err_0 [click here to expand/hide] [link to here]


V43 (0): V1:SIB2_LC_Z_corr_0 [click here to expand/hide] [link to here]


V44 (0): V1:SIB2_LC_Z_0 [click here to expand/hide] [link to here]


V45 (0): V1:SIB2_LC_Y_err_0 [click here to expand/hide] [link to here]


V46 (0): V1:SIB2_LC_Y_corr_0 [click here to expand/hide] [link to here]


V47 (0): V1:SIB2_LC_Y_0 [click here to expand/hide] [link to here]


V48 (0): V1:SIB2_LC_X_err_0 [click here to expand/hide] [link to here]


V49 (0): V1:SIB2_LC_X_corr_0 [click here to expand/hide] [link to here]


V50 (0): V1:SIB2_LC_X_0 [click here to expand/hide] [link to here]


V51 (0): V1:SIB2_LC_TZ_err_0 [click here to expand/hide] [link to here]


V52 (0): V1:SIB2_LC_TZ_corr_0 [click here to expand/hide] [link to here]


V53 (0): V1:SIB2_LC_TZ_0 [click here to expand/hide] [link to here]


V54 (0): V1:SIB2_LC_TY_err_0 [click here to expand/hide] [link to here]


V55 (0): V1:SIB2_LC_TY_corr_0 [click here to expand/hide] [link to here]


V56 (0): V1:SIB2_LC_TY_0 [click here to expand/hide] [link to here]


V57 (0): V1:SIB2_LC_TX_err_0 [click here to expand/hide] [link to here]


V58 (0): V1:SIB2_LC_TX_corr_0 [click here to expand/hide] [link to here]


V59 (0): V1:SIB2_LC_TX_0 [click here to expand/hide] [link to here]


V60 (0): V1:SIB2_LC_LVDT_FR_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V61 (0): V1:SIB2_LC_LVDT_FR_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V62 (0): V1:SIB2_LC_LVDT_FL_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V63 (0): V1:SIB2_LC_LVDT_FL_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V64 (0): V1:SIB2_LC_LVDT_BR_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V65 (0): V1:SIB2_LC_LVDT_BR_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V66 (0): V1:SIB2_LC_LVDT_BL_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V67 (0): V1:SIB2_LC_LVDT_BL_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V68 (0): V1:SIB2_LC_CfgChange_0 [click here to expand/hide] [link to here]


V69 (0): V1:SIB2_LC_COIL_FR_V_0 [click here to expand/hide] [link to here]


V70 (0): V1:SIB2_LC_COIL_FR_H_0 [click here to expand/hide] [link to here]


V71 (0): V1:SIB2_LC_COIL_FL_V_0 [click here to expand/hide] [link to here]


V72 (0): V1:SIB2_LC_COIL_FL_H_0 [click here to expand/hide] [link to here]


V73 (0): V1:SIB2_LC_COIL_BR_V_0 [click here to expand/hide] [link to here]


V74 (0): V1:SIB2_LC_COIL_BR_H_0 [click here to expand/hide] [link to here]


V75 (0): V1:SIB2_LC_COIL_BL_V_0 [click here to expand/hide] [link to here]


V76 (0): V1:SIB2_LC_COIL_BL_H_0 [click here to expand/hide] [link to here]


V77 (0): V1:SIB2_LC_B2_QD2_enbl_safe_0 [click here to expand/hide] [link to here]


V78 (0): V1:SIB2_LC_B2_QD2_enbl_0 [click here to expand/hide] [link to here]


V79 (0): V1:SIB2_LC_B2_QD2_TY_err_0 [click here to expand/hide] [link to here]


V80 (0): V1:SIB2_LC_B2_QD2_TX_err_0 [click here to expand/hide] [link to here]


V81 (0): V1:SIB2_GALVO_gene_sum_0 [click here to expand/hide] [link to here]


V82 (0): V1:SIB2_Clock_100MHz_phi_0 [click here to expand/hide] [link to here]


V83 (0): V1:SIB2_Clock_100MHz_mag_0 [click here to expand/hide] [link to here]


V84 (0): V1:SIB2_B2_QD2_H_norm_0 [click here to expand/hide] [link to here]


V85 (0): V1:SIB2_B2_QD2_GALVO_V_CORR_notsafe_0 [click here to expand/hide] [link to here]


V86 (0): V1:SIB2_B2_QD2_GALVO_V_CORR_0 [click here to expand/hide] [link to here]


V87 (0): V1:SIB2_B2_QD2_GALVO_H_CORR_notsafe_0 [click here to expand/hide] [link to here]


V88 (0): V1:SIB2_B2_QD2_GALVO_H_CORR_0 [click here to expand/hide] [link to here]


V89 (0): V1:SIB2_B2_QD2_8MHz_V_Q_0 [click here to expand/hide] [link to here]


V90 (0): V1:SIB2_B2_QD2_8MHz_V_I_0 [click here to expand/hide] [link to here]


V91 (0): V1:SIB2_B2_QD2_8MHz_SUM_I_0 [click here to expand/hide] [link to here]


V92 (0): V1:SIB2_B2_QD2_8MHz_H_Q_0 [click here to expand/hide] [link to here]


V93 (0): V1:SIB2_B2_QD2_8MHz_H_I_0 [click here to expand/hide] [link to here]


V94 (0): V1:SIB2_B2_QD2_48MHz_V_Q_0 [click here to expand/hide] [link to here]


V95 (0): V1:SIB2_B2_QD2_48MHz_V_I_0 [click here to expand/hide] [link to here]


V96 (0): V1:SIB2_B2_QD2_48MHz_SUM_Q_0 [click here to expand/hide] [link to here]


V97 (0): V1:SIB2_B2_QD2_48MHz_SUM_I_0 [click here to expand/hide] [link to here]


V98 (0): V1:SIB2_B2_QD2_48MHz_H_Q_0 [click here to expand/hide] [link to here]


V99 (0): V1:SIB2_B2_QD2_48MHz_H_I_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr