UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:1 h, 53 min, 57 s
Processing Date:Thu Feb 13 11:42:58 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:825629 sec → 9.556 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (199): V1:SIB2_B2_DC_0 [click here to expand/hide] [link to here]


V1 (194): V1:SIB2_B2_6MHz_I_0 [click here to expand/hide] [link to here]


V2 (192): V1:SIB2_B2_PD1_Blended_0 [click here to expand/hide] [link to here]


V3 (192): V1:SIB2_B2_PD1_Audio_ool_0 [click here to expand/hide] [link to here]


V4 (190): V1:SIB2_B2_PD1_Audio_0 [click here to expand/hide] [link to here]


V5 (178): V1:SIB2_B2_PD1_DC_0 [click here to expand/hide] [link to here]


V6 (165): V1:SDB2_POWERSUPPLY_DBOX_LEFT_DOWN_p12V_0 [click here to expand/hide] [link to here]


V7 (142): V1:SIB2_B2_56MHz_Q_0 [click here to expand/hide] [link to here]


V8 (116): V1:SIB2_B2_56MHz_I_0 [click here to expand/hide] [link to here]


V9 (107): V1:SIB2_B2_PD1_12MHz_mag_0 [click here to expand/hide] [link to here]


V10 (83): V1:SIB2_B2_12MHz_mag_0 [click here to expand/hide] [link to here]


V11 (61): V1:SIB2_B2_PD1_6MHz_Q_0 [click here to expand/hide] [link to here]


V12 (46): V1:SIB2_B2_8MHz_I_0 [click here to expand/hide] [link to here]


V13 (44): V1:SIB2_B2_PD1_8MHz_Q_0 [click here to expand/hide] [link to here]


V14 (42): V1:SIB2_B2_PD1_8MHz_I_0 [click here to expand/hide] [link to here]


V15 (41): V1:SIB2_B2_PD1_6MHz_I_0 [click here to expand/hide] [link to here]


V16 (37): V1:SIB2_B2_PD1_112MHz_mag_0 [click here to expand/hide] [link to here]


V17 (34): V1:SIB2_B2_PD1_112MHz_phi_0 [click here to expand/hide] [link to here]


V18 (31): V1:SIB2_B2_PD1_18MHz_I_0 [click here to expand/hide] [link to here]


V19 (30): V1:SIB2_B2_PD2_112MHz_mag_0 [click here to expand/hide] [link to here]


V20 (29): V1:SIB2_B2_8MHz_Q_0 [click here to expand/hide] [link to here]


V21 (27): V1:SIB2_B2_6MHz_Q_0 [click here to expand/hide] [link to here]


V22 (27): V1:SIB2_B2_112MHz_mag_0 [click here to expand/hide] [link to here]


V23 (26): V1:SIB2_B2_18MHz_I_0 [click here to expand/hide] [link to here]


V24 (14): V1:SIB2_B2_PD2_112MHz_phi_0 [click here to expand/hide] [link to here]


V25 (0): V1:SIB2_B2_PD2_4MHz_mag_0 [click here to expand/hide] [link to here]


V26 (0): V1:SIB2_B2_PD1_VBias_0 [click here to expand/hide] [link to here]


V27 (0): V1:SIB2_B2_PD1_IBias_0 [click here to expand/hide] [link to here]


V28 (0): V1:SIB2_B2_PD1_18MHz_Q_0 [click here to expand/hide] [link to here]


V29 (0): V1:SIB2_B2_PD1_16MHz_phi_0 [click here to expand/hide] [link to here]


V30 (0): V1:SIB2_B2_PD1_16MHz_mag_0 [click here to expand/hide] [link to here]


V31 (0): V1:SIB2_B2_PD1_169MHz_Q_0 [click here to expand/hide] [link to here]


V32 (0): V1:SIB2_B2_PD1_169MHz_I_0 [click here to expand/hide] [link to here]


V33 (0): V1:SIB2_B2_PD1_12MHz_phi_0 [click here to expand/hide] [link to here]


V34 (0): V1:SIB2_B2_18MHz_Q_0 [click here to expand/hide] [link to here]


V35 (0): V1:SIB2_B2_169MHz_Q_0 [click here to expand/hide] [link to here]


V36 (0): V1:SIB2_B2_169MHz_I_0 [click here to expand/hide] [link to here]


V37 (0): V1:SDB_EDB_Tpro_processed_packets_0 [click here to expand/hide] [link to here]


V38 (0): V1:SDB_EDB_Tpro_elapsed_time_0 [click here to expand/hide] [link to here]


V39 (0): V1:SDB2_fast_shutter_sw_0 [click here to expand/hide] [link to here]


V40 (0): V1:SDB2_Tpro_processed_packets_0 [click here to expand/hide] [link to here]


V41 (0): V1:SDB2_Tpro_elapsed_time_0 [click here to expand/hide] [link to here]


V42 (0): V1:SDB2_SBE_elapsed_time_0 [click here to expand/hide] [link to here]


V43 (0): V1:SDB2_SBE_CfgChange_0 [click here to expand/hide] [link to here]


V44 (0): V1:SDB2_Readout_elapsed_time_0 [click here to expand/hide] [link to here]


V45 (0): V1:SDB2_Readout_CfgChange_0 [click here to expand/hide] [link to here]


V46 (0): V1:SDB2_Quadrants_elapsed_time_0 [click here to expand/hide] [link to here]


V47 (0): V1:SDB2_Quadrants_CfgChange_0 [click here to expand/hide] [link to here]


V48 (0): V1:SDB2_Photodiodes_elapsed_time_0 [click here to expand/hide] [link to here]


V49 (0): V1:SDB2_Photodiodes_CfgChange_0 [click here to expand/hide] [link to here]


V50 (0): V1:SDB2_POWERSUPPLY_SWITCH_p12V_0 [click here to expand/hide] [link to here]


V51 (0): V1:SDB2_POWERSUPPLY_QUADRANT_p24V_0 [click here to expand/hide] [link to here]


V52 (0): V1:SDB2_POWERSUPPLY_QUADRANT_p18V_0 [click here to expand/hide] [link to here]


V53 (0): V1:SDB2_POWERSUPPLY_QUADRANT_m18V_0 [click here to expand/hide] [link to here]


V54 (0): V1:SDB2_POWERSUPPLY_DBOX_RIGHT_UP_p12V_0 [click here to expand/hide] [link to here]


V55 (0): V1:SDB2_POWERSUPPLY_DBOX_RIGHT_UP_m12V_0 [click here to expand/hide] [link to here]


V56 (0): V1:SDB2_POWERSUPPLY_DBOX_RIGHT_DOWN_p12V_0 [click here to expand/hide] [link to here]


V57 (0): V1:SDB2_POWERSUPPLY_DBOX_RIGHT_DOWN_m12V_0 [click here to expand/hide] [link to here]


V58 (0): V1:SDB2_POWERSUPPLY_DBOX_LEFT_UP_p12V_0 [click here to expand/hide] [link to here]


V59 (0): V1:SDB2_POWERSUPPLY_DBOX_LEFT_UP_m12V_0 [click here to expand/hide] [link to here]


V60 (0): V1:SDB2_POWERSUPPLY_DBOX_LEFT_DOWN_m12V_0 [click here to expand/hide] [link to here]


V61 (0): V1:SDB2_LC_elapsed_time_0 [click here to expand/hide] [link to here]


V62 (0): V1:SDB2_LC_Z_err_ground_corrected_0 [click here to expand/hide] [link to here]


V63 (0): V1:SDB2_LC_Z_err_0 [click here to expand/hide] [link to here]


V64 (0): V1:SDB2_LC_Z_corr_0 [click here to expand/hide] [link to here]


V65 (0): V1:SDB2_LC_Z_0 [click here to expand/hide] [link to here]


V66 (0): V1:SDB2_LC_Y_err_0 [click here to expand/hide] [link to here]


V67 (0): V1:SDB2_LC_Y_corr_0 [click here to expand/hide] [link to here]


V68 (0): V1:SDB2_LC_Y_0 [click here to expand/hide] [link to here]


V69 (0): V1:SDB2_LC_X_err_0 [click here to expand/hide] [link to here]


V70 (0): V1:SDB2_LC_X_corr_0 [click here to expand/hide] [link to here]


V71 (0): V1:SDB2_LC_X_0 [click here to expand/hide] [link to here]


V72 (0): V1:SDB2_LC_TZ_err_0 [click here to expand/hide] [link to here]


V73 (0): V1:SDB2_LC_TZ_corr_0 [click here to expand/hide] [link to here]


V74 (0): V1:SDB2_LC_TZ_0 [click here to expand/hide] [link to here]


V75 (0): V1:SDB2_LC_TY_err_0 [click here to expand/hide] [link to here]


V76 (0): V1:SDB2_LC_TY_corr_0 [click here to expand/hide] [link to here]


V77 (0): V1:SDB2_LC_TY_0 [click here to expand/hide] [link to here]


V78 (0): V1:SDB2_LC_TX_err_0 [click here to expand/hide] [link to here]


V79 (0): V1:SDB2_LC_TX_corr_0 [click here to expand/hide] [link to here]


V80 (0): V1:SDB2_LC_TX_0 [click here to expand/hide] [link to here]


V81 (0): V1:SDB2_LC_NOISE_flt_0 [click here to expand/hide] [link to here]


V82 (0): V1:SDB2_LC_LVDT_FR_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V83 (0): V1:SDB2_LC_LVDT_FR_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V84 (0): V1:SDB2_LC_LVDT_FL_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V85 (0): V1:SDB2_LC_LVDT_FL_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V86 (0): V1:SDB2_LC_LVDT_BR_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V87 (0): V1:SDB2_LC_LVDT_BR_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V88 (0): V1:SDB2_LC_LVDT_BL_V_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V89 (0): V1:SDB2_LC_LVDT_BL_H_out_raw_1000Hz_0 [click here to expand/hide] [link to here]


V90 (0): V1:SDB2_LC_CfgChange_0 [click here to expand/hide] [link to here]


V91 (0): V1:SDB2_LC_COIL_FR_V_0 [click here to expand/hide] [link to here]


V92 (0): V1:SDB2_LC_COIL_FR_H_0 [click here to expand/hide] [link to here]


V93 (0): V1:SDB2_LC_COIL_FL_V_0 [click here to expand/hide] [link to here]


V94 (0): V1:SDB2_LC_COIL_FL_H_0 [click here to expand/hide] [link to here]


V95 (0): V1:SDB2_LC_COIL_BR_V_0 [click here to expand/hide] [link to here]


V96 (0): V1:SDB2_LC_COIL_BR_H_0 [click here to expand/hide] [link to here]


V97 (0): V1:SDB2_LC_COIL_BL_V_0 [click here to expand/hide] [link to here]


V98 (0): V1:SDB2_LC_COIL_BL_H_0 [click here to expand/hide] [link to here]


V99 (0): V1:SDB2_GALVO_gene_sum_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr