UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:1 h, 43 min, 46 s
Processing Date:Thu Feb 13 11:32:48 2025 (UTC)
Requested start:1420288240 → Tue Jan 7 12:30:22 2025 (UTC)
Requested stop:1421478029 → Tue Jan 21 07:00:11 2025 (UTC)
Requested livetime:825629 sec → 9.556 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 7.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (115): V1:ASC_CMRF_B1_I_0 [click here to expand/hide] [link to here]


V1 (70): V1:ASC_CONTRAST_DEFECT_0 [click here to expand/hide] [link to here]


V2 (56): V1:ASC_PR_TX_INPUT_0 [click here to expand/hide] [link to here]


V3 (55): V1:ASC_PR_TX_IN_0 [click here to expand/hide] [link to here]


V4 (55): V1:ASC_PR_TX_ERR_0 [click here to expand/hide] [link to here]


V5 (55): V1:ASC_PR_TX_0 [click here to expand/hide] [link to here]


V6 (55): V1:ASC_PR_DOF_TX_CORR_0 [click here to expand/hide] [link to here]


V7 (54): V1:ASC_PR_TX_CORR_0 [click here to expand/hide] [link to here]


V8 (27): V1:ASC_DIFFp_TY_OUT_0 [click here to expand/hide] [link to here]


V9 (27): V1:ASC_DIFFp_TY_CORR_0 [click here to expand/hide] [link to here]


V10 (27): V1:ASC_DIFFp_TY_0 [click here to expand/hide] [link to here]


V11 (26): V1:ASC_DIFFp_TY_INPUT_0 [click here to expand/hide] [link to here]


V12 (26): V1:ASC_DIFFp_TY_IN_0 [click here to expand/hide] [link to here]


V13 (26): V1:ASC_DIFFp_TY_ERR_0 [click here to expand/hide] [link to here]


V14 (22): V1:ASC_NE_TY_CORR_0 [click here to expand/hide] [link to here]


V15 (22): V1:ASC_COMMp_TY_OUT_0 [click here to expand/hide] [link to here]


V16 (22): V1:ASC_COMMp_TY_INPUT_0 [click here to expand/hide] [link to here]


V17 (22): V1:ASC_COMMp_TY_IN_0 [click here to expand/hide] [link to here]


V18 (22): V1:ASC_COMMp_TY_HF_0 [click here to expand/hide] [link to here]


V19 (22): V1:ASC_COMMp_TY_ERR_0 [click here to expand/hide] [link to here]


V20 (22): V1:ASC_COMMp_TY_CORR_0 [click here to expand/hide] [link to here]


V21 (22): V1:ASC_COMMp_TY_0 [click here to expand/hide] [link to here]


V22 (19): V1:ASC_PR_DOF_TY_CORR_0 [click here to expand/hide] [link to here]


V23 (17): V1:ASC_DIFFp_TX_OUT_0 [click here to expand/hide] [link to here]


V24 (17): V1:ASC_DIFFp_TX_INPUT_0 [click here to expand/hide] [link to here]


V25 (17): V1:ASC_DIFFp_TX_IN_0 [click here to expand/hide] [link to here]


V26 (17): V1:ASC_DIFFp_TX_ERR_0 [click here to expand/hide] [link to here]


V27 (17): V1:ASC_DIFFp_TX_CORR_0 [click here to expand/hide] [link to here]


V28 (17): V1:ASC_DIFFp_TX_0 [click here to expand/hide] [link to here]


V29 (17): V1:ASC_BS_TY_OUT_0 [click here to expand/hide] [link to here]


V30 (17): V1:ASC_BS_TY_INPUT_0 [click here to expand/hide] [link to here]


V31 (17): V1:ASC_BS_TY_IN_0 [click here to expand/hide] [link to here]


V32 (17): V1:ASC_BS_TY_ERR_0 [click here to expand/hide] [link to here]


V33 (17): V1:ASC_BS_TY_CORR_0 [click here to expand/hide] [link to here]


V34 (17): V1:ASC_BS_TY_0 [click here to expand/hide] [link to here]


V35 (12): V1:ASC_NE_TX_CORR_0 [click here to expand/hide] [link to here]


V36 (12): V1:ASC_COMMp_TX_OUT_0 [click here to expand/hide] [link to here]


V37 (12): V1:ASC_COMMp_TX_INPUT_0 [click here to expand/hide] [link to here]


V38 (12): V1:ASC_COMMp_TX_IN_0 [click here to expand/hide] [link to here]


V39 (12): V1:ASC_COMMp_TX_HF_0 [click here to expand/hide] [link to here]


V40 (12): V1:ASC_COMMp_TX_ERR_0 [click here to expand/hide] [link to here]


V41 (12): V1:ASC_COMMp_TX_CORR_0 [click here to expand/hide] [link to here]


V42 (12): V1:ASC_COMMp_TX_0 [click here to expand/hide] [link to here]


V43 (11): V1:ASC_BS_TX_OUT_0 [click here to expand/hide] [link to here]


V44 (11): V1:ASC_BS_TX_INPUT_0 [click here to expand/hide] [link to here]


V45 (0): V1:ASC_PR_TX_NOISE_0 [click here to expand/hide] [link to here]


V46 (0): V1:ASC_PR_TX_ENBL_0 [click here to expand/hide] [link to here]


V47 (0): V1:ASC_PR_TX_B4_12MHz_ENBL_0 [click here to expand/hide] [link to here]


V48 (0): V1:ASC_PR_DOF_Y_CORR_0 [click here to expand/hide] [link to here]


V49 (0): V1:ASC_PR_DOF_X_CORR_0 [click here to expand/hide] [link to here]


V50 (0): V1:ASC_PR_DOF_TY_NOISE_0 [click here to expand/hide] [link to here]


V51 (0): V1:ASC_PR_DOF_TX_NOISE_0 [click here to expand/hide] [link to here]


V52 (0): V1:ASC_NOISE_0 [click here to expand/hide] [link to here]


V53 (0): V1:ASC_NI_TY_ON_0 [click here to expand/hide] [link to here]


V54 (0): V1:ASC_NI_TY_NOISE_0 [click here to expand/hide] [link to here]


V55 (0): V1:ASC_NI_TY_CORR_0 [click here to expand/hide] [link to here]


V56 (0): V1:ASC_NI_TX_ON_0 [click here to expand/hide] [link to here]


V57 (0): V1:ASC_NI_TX_NOISE_0 [click here to expand/hide] [link to here]


V58 (0): V1:ASC_NI_TX_CORR_0 [click here to expand/hide] [link to here]


V59 (0): V1:ASC_NE_TY_ON_0 [click here to expand/hide] [link to here]


V60 (0): V1:ASC_NE_TY_NOISE_0 [click here to expand/hide] [link to here]


V61 (0): V1:ASC_NE_TX_ON_0 [click here to expand/hide] [link to here]


V62 (0): V1:ASC_NE_TX_NOISE_0 [click here to expand/hide] [link to here]


V63 (0): V1:ASC_ENABLE_0 [click here to expand/hide] [link to here]


V64 (0): V1:ASC_DITHER_TY_ON_0 [click here to expand/hide] [link to here]


V65 (0): V1:ASC_DITHER_TY_ENBL_0 [click here to expand/hide] [link to here]


V66 (0): V1:ASC_DITHER_TX_ON_0 [click here to expand/hide] [link to here]


V67 (0): V1:ASC_DITHER_TX_ENBL_0 [click here to expand/hide] [link to here]


V68 (0): V1:ASC_DIFFp_TY_TRIG_0 [click here to expand/hide] [link to here]


V69 (0): V1:ASC_DIFFp_TY_NOISE_0 [click here to expand/hide] [link to here]


V70 (0): V1:ASC_DIFFp_TY_ENBL_0 [click here to expand/hide] [link to here]


V71 (0): V1:ASC_DIFFp_TX_TRIG_0 [click here to expand/hide] [link to here]


V72 (0): V1:ASC_DIFFp_TX_NOISE_0 [click here to expand/hide] [link to here]


V73 (0): V1:ASC_DIFFp_TX_ENBL_0 [click here to expand/hide] [link to here]


V74 (0): V1:ASC_DIFFm_TY_INPUT_0 [click here to expand/hide] [link to here]


V75 (0): V1:ASC_DIFFm_TX_INPUT_0 [click here to expand/hide] [link to here]


V76 (0): V1:ASC_COMMp_TY_TRIG_0 [click here to expand/hide] [link to here]


V77 (0): V1:ASC_COMMp_TY_NOISE_0 [click here to expand/hide] [link to here]


V78 (0): V1:ASC_COMMp_TY_LF_0 [click here to expand/hide] [link to here]


V79 (0): V1:ASC_COMMp_TY_ENBL_0 [click here to expand/hide] [link to here]


V80 (0): V1:ASC_COMMp_TX_TRIG_0 [click here to expand/hide] [link to here]


V81 (0): V1:ASC_COMMp_TX_NOISE_0 [click here to expand/hide] [link to here]


V82 (0): V1:ASC_COMMp_TX_LF_0 [click here to expand/hide] [link to here]


V83 (0): V1:ASC_COMMp_TX_ENBL_0 [click here to expand/hide] [link to here]


V84 (0): V1:ASC_COMMp_BL_TY_0 [click here to expand/hide] [link to here]


V85 (0): V1:ASC_COMMp_BL_TX_0 [click here to expand/hide] [link to here]


V86 (0): V1:ASC_COMMm_TY_INPUT_0 [click here to expand/hide] [link to here]


V87 (0): V1:ASC_COMMm_TX_INPUT_0 [click here to expand/hide] [link to here]


V88 (0): V1:ASC_COLOR_0 [click here to expand/hide] [link to here]


V89 (0): V1:ASC_CMRF_B1_mag_0 [click here to expand/hide] [link to here]


V90 (0): V1:ASC_BS_TY_TRIG_0 [click here to expand/hide] [link to here]


V91 (0): V1:ASC_BS_TY_SSFS_LF_Q_ENBL_0 [click here to expand/hide] [link to here]


V92 (0): V1:ASC_BS_TY_ON_0 [click here to expand/hide] [link to here]


V93 (0): V1:ASC_BS_TY_NOISE_0 [click here to expand/hide] [link to here]


V94 (0): V1:ASC_BS_TY_LF_0 [click here to expand/hide] [link to here]


V95 (0): V1:ASC_BS_TY_ENBL_0 [click here to expand/hide] [link to here]


V96 (0): V1:ASC_BS_TX_TRIG_0 [click here to expand/hide] [link to here]


V97 (0): V1:ASC_BS_TX_ON_0 [click here to expand/hide] [link to here]


V98 (0): V1:ASC_BS_TX_NOISE_0 [click here to expand/hide] [link to here]


V99 (0): V1:ASC_BS_TX_LF_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr