UPV analysis over V1:Hrec_hoft_16384Hz


upv ./segments.txt ./parameters.txt 

Summary

UPV version:3.2.0: documentation gitlab repository
UPV run by:unknown
UPV processing time:2 h, 32 min, 44 s
Processing Date:Fri Feb 21 14:34:10 2025 (UTC)
Requested start:1407499998 → Mon Aug 12 12:13:00 2024 (UTC)
Requested stop:1408708852 → Mon Aug 26 12:00:34 2024 (UTC)
Requested livetime:950208 sec → 10.998 days
Requested segments:upv.insegments.txt
Summary text file:upv.summary.txt
Number of source channels:100 (out of 100)

Parameters

Configuration:upv.parameters.txt
Target SNR selection:SNR > 6.000
Target frequency selection:16.000 Hz < f < 1956.764 Hz
Coincidence time window:δt = 1.000 s
Veto definition:use-percentage > 0.400 (per frequency bin)
number of used source clusters > 10 (per frequency bin)

Target = V1:Hrec_hoft_16384Hz

Note: these plots includes the triggers used in the VetoPerf report: the selection can be different from the one used for UPV.


Veto performance

The veto performance has been measured. See the VetoPerf report.


V0 (994): V1:Sc_NE_MIR_Z_CORR_LN_0 [click here to expand/hide] [link to here]


V1 (989): V1:Sc_NE_MIR_LSC_CORR_0 [click here to expand/hide] [link to here]


V2 (987): V1:Sc_NE_MIR_VOUT_UR_0 [click here to expand/hide] [link to here]


V3 (980): V1:Sc_NE_MIR_Z_CORR_0 [click here to expand/hide] [link to here]


V4 (964): V1:Sc_NE_MIR_VOUT_UL_0 [click here to expand/hide] [link to here]


V5 (910): V1:Sc_NE_MIR_VOUT_DL_0 [click here to expand/hide] [link to here]


V6 (909): V1:Sc_NE_MIR_VOUT_DR_0 [click here to expand/hide] [link to here]


V7 (326): V1:Sc_NE_MIR_X_AA_0 [click here to expand/hide] [link to here]


V8 (251): V1:Sc_NE_MIR_Y_AA_0 [click here to expand/hide] [link to here]


V9 (154): V1:Sc_MC_RFC_Err_Post_0 [click here to expand/hide] [link to here]


V10 (153): V1:Sc_MC_RFC_Err_Pre_0 [click here to expand/hide] [link to here]


V11 (153): V1:Sc_MC_MIR_Z_CORR_0 [click here to expand/hide] [link to here]


V12 (126): V1:Sc_MC_txE_p_0 [click here to expand/hide] [link to here]


V13 (60): V1:Sc_NE_MAR_TY_CORR_0 [click here to expand/hide] [link to here]


V14 (39): V1:Sc_MC_RM_MIR_TY_0 [click here to expand/hide] [link to here]


V15 (23): V1:Sc_NE_tyAA_0 [click here to expand/hide] [link to here]


V16 (13): V1:Sc_NE_txAA_0 [click here to expand/hide] [link to here]


V17 (0): V1:Sc_NI_MAR_PSDT_PWR_0 [click here to expand/hide] [link to here]


V18 (0): V1:Sc_NI_MAR_PSDM_Y2_0 [click here to expand/hide] [link to here]


V19 (0): V1:Sc_NI_MAR_PSDM_Y1_0 [click here to expand/hide] [link to here]


V20 (0): V1:Sc_NI_MAR_PSDM_X2_0 [click here to expand/hide] [link to here]


V21 (0): V1:Sc_NI_MAR_PSDM_X1_0 [click here to expand/hide] [link to here]


V22 (0): V1:Sc_NI_MAR_PSDM_PWR_0 [click here to expand/hide] [link to here]


V23 (0): V1:Sc_NI_MAR_COIL_FLAG_0 [click here to expand/hide] [link to here]


V24 (0): V1:Sc_NI_LOCK_FLAG_0 [click here to expand/hide] [link to here]


V25 (0): V1:Sc_NI_F7_Z_0 [click here to expand/hide] [link to here]


V26 (0): V1:Sc_NI_F7_Y_0 [click here to expand/hide] [link to here]


V27 (0): V1:Sc_NI_F7_X_0 [click here to expand/hide] [link to here]


V28 (0): V1:Sc_NI_F7_TZ_CORR_0 [click here to expand/hide] [link to here]


V29 (0): V1:Sc_NI_F7_TZ_0 [click here to expand/hide] [link to here]


V30 (0): V1:Sc_NI_F7_TY_CORR_0 [click here to expand/hide] [link to here]


V31 (0): V1:Sc_NI_F7_TY_0 [click here to expand/hide] [link to here]


V32 (0): V1:Sc_NI_F7_TX_CORR_0 [click here to expand/hide] [link to here]


V33 (0): V1:Sc_NI_F7_TX_0 [click here to expand/hide] [link to here]


V34 (0): V1:Sc_NI_F7_LVDT_V3_0 [click here to expand/hide] [link to here]


V35 (0): V1:Sc_NI_F7_LVDT_V2_0 [click here to expand/hide] [link to here]


V36 (0): V1:Sc_NI_F7_LVDT_V1_0 [click here to expand/hide] [link to here]


V37 (0): V1:Sc_NI_F7_LVDT_H3_0 [click here to expand/hide] [link to here]


V38 (0): V1:Sc_NI_F7_LVDT_H2_0 [click here to expand/hide] [link to here]


V39 (0): V1:Sc_NI_F7_LVDT_H1_0 [click here to expand/hide] [link to here]


V40 (0): V1:Sc_NI_F7_COIL_V3_0 [click here to expand/hide] [link to here]


V41 (0): V1:Sc_NI_F7_COIL_V2_0 [click here to expand/hide] [link to here]


V42 (0): V1:Sc_NI_F7_COIL_V1_0 [click here to expand/hide] [link to here]


V43 (0): V1:Sc_NI_F7_COIL_H3_0 [click here to expand/hide] [link to here]


V44 (0): V1:Sc_NI_F7_COIL_H2_0 [click here to expand/hide] [link to here]


V45 (0): V1:Sc_NI_F7_COIL_H1_0 [click here to expand/hide] [link to here]


V46 (0): V1:Sc_NE_noise_0 [click here to expand/hide] [link to here]


V47 (0): V1:Sc_NE_NA_Cty_0 [click here to expand/hide] [link to here]


V48 (0): V1:Sc_NE_NA_Ctx_0 [click here to expand/hide] [link to here]


V49 (0): V1:Sc_NE_MIR_Z_0 [click here to expand/hide] [link to here]


V50 (0): V1:Sc_NE_MIR_TY_0 [click here to expand/hide] [link to here]


V51 (0): V1:Sc_NE_MIR_TX_0 [click here to expand/hide] [link to here]


V52 (0): V1:Sc_NE_MIR_PSDI_Y2_0 [click here to expand/hide] [link to here]


V53 (0): V1:Sc_NE_MIR_PSDI_X2_0 [click here to expand/hide] [link to here]


V54 (0): V1:Sc_NE_MIR_PSDI_PWR_0 [click here to expand/hide] [link to here]


V55 (0): V1:Sc_NE_MIR_PSDF_Y2_0 [click here to expand/hide] [link to here]


V56 (0): V1:Sc_NE_MIR_PSDF_Y1_0 [click here to expand/hide] [link to here]


V57 (0): V1:Sc_NE_MIR_PSDF_X2_0 [click here to expand/hide] [link to here]


V58 (0): V1:Sc_NE_MIR_PSDF_X1_0 [click here to expand/hide] [link to here]


V59 (0): V1:Sc_NE_MIR_PSDF_PWR_0 [click here to expand/hide] [link to here]


V60 (0): V1:Sc_NE_MIR_COIL_FLAG_0 [click here to expand/hide] [link to here]


V61 (0): V1:Sc_NE_MAR_Y_CORR_0 [click here to expand/hide] [link to here]


V62 (0): V1:Sc_NE_MAR_TZ_CORR_0 [click here to expand/hide] [link to here]


V63 (0): V1:Sc_NE_MAR_TZ_0 [click here to expand/hide] [link to here]


V64 (0): V1:Sc_NE_MAR_TY_T_0 [click here to expand/hide] [link to here]


V65 (0): V1:Sc_NE_MAR_TY_0 [click here to expand/hide] [link to here]


V66 (0): V1:Sc_NE_MAR_TX_CORR_0 [click here to expand/hide] [link to here]


V67 (0): V1:Sc_NE_MAR_TX_0 [click here to expand/hide] [link to here]


V68 (0): V1:Sc_NE_MAR_PSDT_Y2_0 [click here to expand/hide] [link to here]


V69 (0): V1:Sc_NE_MAR_PSDT_Y1_0 [click here to expand/hide] [link to here]


V70 (0): V1:Sc_NE_MAR_PSDT_X1_0 [click here to expand/hide] [link to here]


V71 (0): V1:Sc_NE_MAR_PSDT_PWR_0 [click here to expand/hide] [link to here]


V72 (0): V1:Sc_NE_MAR_PSDM_Y2_0 [click here to expand/hide] [link to here]


V73 (0): V1:Sc_NE_MAR_PSDM_Y1_0 [click here to expand/hide] [link to here]


V74 (0): V1:Sc_NE_MAR_PSDM_X2_0 [click here to expand/hide] [link to here]


V75 (0): V1:Sc_NE_MAR_PSDM_X1_0 [click here to expand/hide] [link to here]


V76 (0): V1:Sc_NE_MAR_PSDM_PWR_0 [click here to expand/hide] [link to here]


V77 (0): V1:Sc_NE_MAR_COIL_FLAG_0 [click here to expand/hide] [link to here]


V78 (0): V1:Sc_NE_F7_Z_CORR_0 [click here to expand/hide] [link to here]


V79 (0): V1:Sc_NE_F7_Z_0 [click here to expand/hide] [link to here]


V80 (0): V1:Sc_NE_F7_Y_0 [click here to expand/hide] [link to here]


V81 (0): V1:Sc_NE_F7_X_0 [click here to expand/hide] [link to here]


V82 (0): V1:Sc_NE_F7_TZ_CORR_0 [click here to expand/hide] [link to here]


V83 (0): V1:Sc_NE_F7_TZ_0 [click here to expand/hide] [link to here]


V84 (0): V1:Sc_NE_F7_TY_CORR_0 [click here to expand/hide] [link to here]


V85 (0): V1:Sc_NE_F7_TY_0 [click here to expand/hide] [link to here]


V86 (0): V1:Sc_NE_F7_TX_CORR_0 [click here to expand/hide] [link to here]


V87 (0): V1:Sc_NE_F7_TX_0 [click here to expand/hide] [link to here]


V88 (0): V1:Sc_NE_F7_LVDT_V3_0 [click here to expand/hide] [link to here]


V89 (0): V1:Sc_NE_F7_LVDT_V2_0 [click here to expand/hide] [link to here]


V90 (0): V1:Sc_NE_F7_LVDT_V1_0 [click here to expand/hide] [link to here]


V91 (0): V1:Sc_NE_F7_LVDT_H3_0 [click here to expand/hide] [link to here]


V92 (0): V1:Sc_NE_F7_LVDT_H2_0 [click here to expand/hide] [link to here]


V93 (0): V1:Sc_NE_F7_LVDT_H1_0 [click here to expand/hide] [link to here]


V94 (0): V1:Sc_NE_ErrPost_0 [click here to expand/hide] [link to here]


V95 (0): V1:Sc_MC_noise_0 [click here to expand/hide] [link to here]


V96 (0): V1:Sc_MC_SSFS_ON_0 [click here to expand/hide] [link to here]


V97 (0): V1:Sc_MC_RM_TZ_0 [click here to expand/hide] [link to here]


V98 (0): V1:Sc_MC_RM_TY_0 [click here to expand/hide] [link to here]


V99 (0): V1:Sc_MC_RFC_On_0 [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr