OUTPUT  DIRECTORY  ./report
OUTPUT  VERBOSITY  1

TARGET  OMICRON    V1:Hrec_hoft_16384Hz
TARGET  CLUSTERDT  0.1
TARGET  SNRMIN     6

COINC   TIMEWIN    1.0

VETO    UPMIN      0.4
VETO    UMIN       10
VETO    PRINT      0
VETO    PERF       5  8  10  20
VETO    PERFPRINT  1  0

SOURCE  CLUSTERDT  0.1
SOURCE  OMICRON    V1:SBE_SWEB_F1_y_LVDT_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_GEO_GRNS_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_GEO_GRV_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_GEO_GRWE_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_GEO_X_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_LVDT_F0H0_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_LVDT_F0H1_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_LVDT_F0H2_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_LVDT_F0V_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_LVDT_F1V_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_NbSa_F0_z_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_SA_F0_diff_LVDT_z_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_TRIL_X_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_TRIL_Y_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_TRIL_Z_raw_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act0_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act1_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act2_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act3_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act_ty_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act_x_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act_y_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_act_z_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_actty_test_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_actx_test_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_acty_test_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_actz_test_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_diff_bench_MIR_z_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_diff_speed_bench_MIR_z_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_hor_safety_500Hz
SOURCE  OMICRON    V1:SBE_SWEB_vert_safety_500Hz
SOURCE  OMICRON    V1:SDB1_B1_DARM_TX_offset
SOURCE  OMICRON    V1:SDB1_B1_DARM_TY_offset
SOURCE  OMICRON    V1:SDB1_B1_PD3_DC_norm_B1p
SOURCE  OMICRON    V1:SDB1_B1_PD3_DC_norm_B1p_sw
SOURCE  OMICRON    V1:SDB1_B1_PD3_DC_norm_B1s
SOURCE  OMICRON    V1:SDB1_B1_PD3_f1_i
SOURCE  OMICRON    V1:SDB1_B1_PD3_f1_i_DCn
SOURCE  OMICRON    V1:SDB1_B1_PD3_f1_q
SOURCE  OMICRON    V1:SDB1_B1_f1_DARM_DCn_i
SOURCE  OMICRON    V1:SDB1_B1_f1_DARM_DCn_q
SOURCE  OMICRON    V1:SDB1_B1_f1_i
SOURCE  OMICRON    V1:SDB1_B1_f1_i_DCn
SOURCE  OMICRON    V1:SDB1_B1_f1_q
SOURCE  OMICRON    V1:SDB1_B1s_f1_i
SOURCE  OMICRON    V1:SDB1_B1s_f1_q
SOURCE  OMICRON    V1:SDB1_B1x_DC_DARM_i
SOURCE  OMICRON    V1:SDB1_B1x_DC_DARM_q
SOURCE  OMICRON    V1:SDB1_B1x_f1_DARM_i
SOURCE  OMICRON    V1:SDB1_B1x_f1_DARM_i_DC2n
SOURCE  OMICRON    V1:SDB1_B1x_f1_DARM_i_DCn
SOURCE  OMICRON    V1:SDB1_B1x_f1_DARM_q
SOURCE  OMICRON    V1:SDB1_B1x_f1_i_DC2n_err
SOURCE  OMICRON    V1:SDB1_B1x_f1_i_DCn
SOURCE  OMICRON    V1:SDB1_B1x_f1_i_n
SOURCE  OMICRON    V1:SDB1_B5_QD1_H
SOURCE  OMICRON    V1:SDB1_B5_QD1_V
SOURCE  OMICRON    V1:SDB1_B5_QD1_sum
SOURCE  OMICRON    V1:SDB1_B5_QD2_H
SOURCE  OMICRON    V1:SDB1_B5_QD2_H_offset
SOURCE  OMICRON    V1:SDB1_B5_QD2_H_pre
SOURCE  OMICRON    V1:SDB1_B5_QD2_TX_err
SOURCE  OMICRON    V1:SDB1_B5_QD2_TY_err
SOURCE  OMICRON    V1:SDB1_B5_QD2_V
SOURCE  OMICRON    V1:SDB1_B5_QD2_V_offset
SOURCE  OMICRON    V1:SDB1_B5_QD2_V_pre
SOURCE  OMICRON    V1:SDB1_B5_QD2_safe
SOURCE  OMICRON    V1:SDB1_B5_QD2_sum
SOURCE  OMICRON    V1:SDB1_FAST_SHUTTER_CfgChange
SOURCE  OMICRON    V1:SDB1_FAST_SHUTTER_elapsed_time
SOURCE  OMICRON    V1:SDB1_FI_CfgChange
SOURCE  OMICRON    V1:SDB1_FI_elapsed_time
SOURCE  OMICRON    V1:SDB1_FI_in
SOURCE  OMICRON    V1:SDB1_LC_B1_DARM_enbl
SOURCE  OMICRON    V1:SDB1_LC_B1s_QD2_enbl_safe
SOURCE  OMICRON    V1:SDB1_LC_B5_QD2_enbl
SOURCE  OMICRON    V1:SDB1_LC_B5_QD2_enbl_safe
SOURCE  OMICRON    V1:SDB1_LC_COIL_BL_H
SOURCE  OMICRON    V1:SDB1_LC_COIL_BL_V
SOURCE  OMICRON    V1:SDB1_LC_COIL_BR_H
SOURCE  OMICRON    V1:SDB1_LC_COIL_BR_V
SOURCE  OMICRON    V1:SDB1_LC_COIL_FL_H
SOURCE  OMICRON    V1:SDB1_LC_COIL_FL_V
SOURCE  OMICRON    V1:SDB1_LC_COIL_FR_H
SOURCE  OMICRON    V1:SDB1_LC_COIL_FR_V
SOURCE  OMICRON    V1:SDB1_LC_COIL_disable_inv
SOURCE  OMICRON    V1:SDB1_LC_CfgChange
SOURCE  OMICRON    V1:SDB1_LC_LVDT_BL_H_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_BL_V_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_BR_H_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_BR_V_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_FL_H_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_FL_V_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_FR_H_err
SOURCE  OMICRON    V1:SDB1_LC_LVDT_FR_V_err
SOURCE  OMICRON    V1:SDB1_LC_TX
SOURCE  OMICRON    V1:SDB1_LC_TXYZ_enbl
SOURCE  OMICRON    V1:SDB1_LC_TXY_floating_enbl
SOURCE  OMICRON    V1:SDB1_LC_TX_corr
SOURCE  OMICRON    V1:SDB1_LC_TX_err