VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:3 h, 46 min, 56 s
Processing Date:Fri Jan 19 15:50:07 2024 (UTC)
Requested start:1387467885 → Sun Dec 24 15:44:27 2023 (UTC)
Requested stop:1388080814 → Sun Dec 31 17:59:56 2023 (UTC)
Requested livetime:452627 sec → 5.239 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:4316241
Number of raw clusters:71452
Number of active clusters:71452 (SNR > 5.000) 592 (SNR > 8.000) 470 (SNR > 10.000) 402 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (452627 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 71452 clusters
V0 → V1:LSC_DARM_0, vetoed clusters: 1101 (1.541 %)
V1 → V1:LSC_DARM_ERR_0, vetoed clusters: 1066 (1.492 %)
V2 → V1:LSC_DARM_CORR_raw_0, vetoed clusters: 1014 (1.419 %)
V3 → V1:LSC_DARM_INPUT_0, vetoed clusters: 973 (1.362 %)
V4 → V1:LSC_DCP_DARM_CORR_FLT_LF_0, vetoed clusters: 660 (0.924 %)
V5 → V1:LSC_DCP_DARM_ERR_FLT_HF_0, vetoed clusters: 608 (0.851 %)
V6 → V1:LSC_DCP_DARM_ERR_FLT_HF_DEL_0, vetoed clusters: 561 (0.785 %)
V7 → V1:LSC_DCP_DARM_ERR_FLT_LF_0, vetoed clusters: 510 (0.714 %)
V8 → V1:LSC_DCP_DARM_ERR_FLT_LF_DEL_0, vetoed clusters: 484 (0.677 %)
V9 → V1:LSC_DCP_MM_RE_0, vetoed clusters: 430 (0.602 %)

V0: V1:LSC_DARM_0 (ε = 1.541%, ε/d = 580.989) [click here to expand/hide] [link to here]


V1: V1:LSC_DARM_ERR_0 (ε = 1.492%, ε/d = 587.097) [click here to expand/hide] [link to here]


V2: V1:LSC_DARM_CORR_raw_0 (ε = 1.419%, ε/d = 600.765) [click here to expand/hide] [link to here]


V3: V1:LSC_DARM_INPUT_0 (ε = 1.362%, ε/d = 615.940) [click here to expand/hide] [link to here]


V4: V1:LSC_DCP_DARM_CORR_FLT_LF_0 (ε = 0.924%, ε/d = 790.965) [click here to expand/hide] [link to here]


V5: V1:LSC_DCP_DARM_ERR_FLT_HF_0 (ε = 0.851%, ε/d = 833.194) [click here to expand/hide] [link to here]


V6: V1:LSC_DCP_DARM_ERR_FLT_HF_DEL_0 (ε = 0.785%, ε/d = 862.669) [click here to expand/hide] [link to here]


V7: V1:LSC_DCP_DARM_ERR_FLT_LF_0 (ε = 0.714%, ε/d = 928.976) [click here to expand/hide] [link to here]


V8: V1:LSC_DCP_DARM_ERR_FLT_LF_DEL_0 (ε = 0.677%, ε/d = 933.871) [click here to expand/hide] [link to here]


V9: V1:LSC_DCP_MM_RE_0 (ε = 0.602%, ε/d = 1014.021) [click here to expand/hide] [link to here]


V10: V1:LSC_DARM_CORR_0 (ε = 0.600%, ε/d = 1751.578) [click here to expand/hide] [link to here]


V11: V1:LSC_DCP_DARM_CORR_FLT_HF_0 (ε = 0.582%, ε/d = 1033.521) [click here to expand/hide] [link to here]


V12: V1:LSC_DCP_NORM_0 (ε = 0.509%, ε/d = 1049.129) [click here to expand/hide] [link to here]


V13: V1:LSC_DCP_MM_IM_0 (ε = 0.472%, ε/d = 1115.503) [click here to expand/hide] [link to here]


V14: V1:LSC_B4_DC_FRINGE_0 (ε = 0.014%, ε/d = 417.739) [click here to expand/hide] [link to here]


V15: V1:LSC_B4_DC_OLD_NORM_0 (ε = 0.014%, ε/d = 417.739) [click here to expand/hide] [link to here]


V16: V1:LSC_B4_DC_SQ_0 (ε = 0.014%, ε/d = 376.784) [click here to expand/hide] [link to here]


V17: V1:LSC_B7_B8_6MHz_I_SUM_0 (ε = 0.011%, ε/d = 523.597) [click here to expand/hide] [link to here]


V18: V1:LSC_B7_B8_6MHz_I_SUM_COMP_0 (ε = 0.011%, ε/d = 500.417) [click here to expand/hide] [link to here]


V19: V1:LSC_B7_B8_6MHz_I_SUM_NORM_0 (ε = 0.011%, ε/d = 500.417) [click here to expand/hide] [link to here]


V20: V1:LSC_B4_112MHz_MAG_TRIG_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V21: V1:LSC_B4_12MHz_MAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V22: V1:LSC_B4_12MHz_MAG_GRAD_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V23: V1:LSC_B4_12MHz_MAG_GRAD_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V24: V1:LSC_B4_12MHz_MAG_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V25: V1:LSC_B4_12MHz_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V26: V1:LSC_B4_12MHz_MAG_TRIG_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V27: V1:LSC_B4_6MHz_I_COMP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V28: V1:LSC_B4_DC_LP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V29: V1:LSC_B4_DC_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V30: V1:LSC_B4_DC_TRIG_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V31: V1:LSC_B5_112MHz_MAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V32: V1:LSC_B5_112MHz_MAG_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V33: V1:LSC_B5_112MHz_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V34: V1:LSC_B5_12MHz_MAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V35: V1:LSC_B5_12MHz_MAG_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V36: V1:LSC_B5_12MHz_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V37: V1:LSC_B5_DC_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:LSC_B7_B8_DC_DIF_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:LSC_B7_B8_DC_DIF_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:LSC_B7_B8_DC_SUM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:LSC_B7_B8_DC_SUM_SQRT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:LSC_BS_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:LSC_BS_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:LSC_CARM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:LSC_CARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:LSC_CARM_DARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:LSC_CARM_DARM_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:LSC_CARM_DARM_flt_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:LSC_CARM_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:LSC_CARM_FAST_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:LSC_CARM_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:LSC_CARM_MC_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:LSC_CARM_MC_ERR_FAKE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:LSC_CARM_MC_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:LSC_CARM_MC_INPUT_FAKE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:LSC_CARM_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:LSC_CARM_SLOW_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:LSC_CARM_SLOW_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:LSC_CARM_SLOW_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:LSC_CARM_SLOW_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:LSC_CARM_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:LSC_DARM_FREQ_ZEROED_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:LSC_DARM_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:LSC_DARM_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:LSC_DRMI_TRIGGER_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:LSC_DRMI_TRIGGER_IN1_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:LSC_DRMI_TRIGGER_IN2_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:LSC_DRMI_TRIGGER_IN3_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:LSC_DRMI_TRIGGER_IN4_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:LSC_DRMI_TRIGGER_IN4_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:LSC_ENABLE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:LSC_ENV_MAG_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:LSC_ENV_MAG_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:LSC_ENV_MAG_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:LSC_ENV_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:LSC_Etalon_Acl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:LSC_GREEN_LOCK_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:LSC_GREEN_LOCK_CHECK_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:LSC_GREEN_OFF_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:LSC_LSC_ARMS_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:LSC_MICH_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:LSC_MICH_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:LSC_MICH_DARM_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:LSC_MICH_DARM_flt_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:LSC_MICH_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:LSC_MICH_FILTER_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:LSC_MICH_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:LSC_MICH_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:LSC_MICH_SET_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:LSC_MICH_SET_CORR_CLIP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:LSC_MICH_SET_CORR_FLT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:LSC_MICH_SET_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:LSC_MICH_SET_EN_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:LSC_MICH_SET_IN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:LSC_MICH_SET_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:LSC_MICH_SET_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:LSC_MICH_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:LSC_MICH_TRIGGER_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:LSC_MICH_TRIGGER_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr