VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:2 h, 27 min, 40 s
Processing Date:Fri Jan 19 14:30:59 2024 (UTC)
Requested start:1387467885 → Sun Dec 24 15:44:27 2023 (UTC)
Requested stop:1388080814 → Sun Dec 31 17:59:56 2023 (UTC)
Requested livetime:452627 sec → 5.239 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:4316241
Number of raw clusters:71452
Number of active clusters:71452 (SNR > 5.000) 592 (SNR > 8.000) 470 (SNR > 10.000) 402 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (452627 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 71452 clusters
V0 → V1:LSC_B1_DC_IN2_0, vetoed clusters: 1112 (1.556 %)
V1 → V1:LSC_B1_DC_INPUT_0, vetoed clusters: 1112 (1.556 %)
V2 → V1:LSC_B1_DC_IN1_0, vetoed clusters: 1105 (1.546 %)
V3 → V1:LSC_B2_6MHz_I_ARM_0, vetoed clusters: 15 (0.021 %)
V4 → V1:LSC_B1p_56MHz_I_ARM_NORM_0, vetoed clusters: 10 (0.014 %)
V5 → V1:LSC_B2_6MHz_I_ARM_NORM_0, vetoed clusters: 10 (0.014 %)
V6 → V1:LSC_B1B4_DIF_0, vetoed clusters: 10 (0.014 %)
V7 → V1:LSC_B2_DC_OLD_NORM_0, vetoed clusters: 10 (0.014 %)
V8 → V1:LSC_B1B4_SUM_0, vetoed clusters: 10 (0.014 %)

V0: V1:LSC_B1_DC_IN2_0 (ε = 1.556%, ε/d = 581.439) [click here to expand/hide] [link to here]


V1: V1:LSC_B1_DC_INPUT_0 (ε = 1.556%, ε/d = 581.439) [click here to expand/hide] [link to here]


V2: V1:LSC_B1_DC_IN1_0 (ε = 1.546%, ε/d = 571.806) [click here to expand/hide] [link to here]


V3: V1:LSC_B2_6MHz_I_ARM_0 (ε = 0.021%, ε/d = 290.899) [click here to expand/hide] [link to here]


V4: V1:LSC_B1p_56MHz_I_ARM_NORM_0 (ε = 0.014%, ε/d = 436.156) [click here to expand/hide] [link to here]


V5: V1:LSC_B2_6MHz_I_ARM_NORM_0 (ε = 0.014%, ε/d = 335.944) [click here to expand/hide] [link to here]


V6: V1:LSC_B1B4_DIF_0 (ε = 0.014%, ε/d = 411.772) [click here to expand/hide] [link to here]


V7: V1:LSC_B2_DC_OLD_NORM_0 (ε = 0.014%, ε/d = 411.772) [click here to expand/hide] [link to here]


V8: V1:LSC_B1B4_SUM_0 (ε = 0.014%, ε/d = 368.711) [click here to expand/hide] [link to here]


V9: V1:ISC_Tpro_processed_packets_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V10: V1:ISYS_Acl_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V11: V1:ISYS_Acl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V12: V1:ISYS_EER_FastDac_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V13: V1:ISYS_EER_FastDac_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V14: V1:ISYS_EER_dac_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V15: V1:ISYS_EER_dac_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V16: V1:ISYS_moni_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V17: V1:ISYS_moni_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V18: V1:ISYS_slow_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V19: V1:ISYS_slow_pre_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V20: V1:ISYS_slow_pre_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V21: V1:ISYSnoise_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V22: V1:ISYSnoise_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V23: V1:LFC_AOM_LOOP_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V24: V1:LFC_AOM_LOOP_DC1_sw_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V25: V1:LFC_AOM_LOOP_DC2_sw_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V26: V1:LFC_AOM_LOOP_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V27: V1:LFC_AOM_LOOP_GAIN_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V28: V1:LFC_AOM_LOOP_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V29: V1:LFC_AOM_LOOP_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V30: V1:LFC_AOM_LOOP_PRE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V31: V1:LFC_AOM_LOOP_SET_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V32: V1:LFC_Ctrl_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V33: V1:LFC_Ctrl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V34: V1:LFC_GR_PD_DC_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V35: V1:LFC_GR_PD_RF_5MHz_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V36: V1:LFC_GR_PD_RF_5MHz_I_CAL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V37: V1:LFC_GR_PD_RF_5MHz_I_FIL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:LFC_GR_PD_RF_5MHz_I_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:LFC_LOCK_FLAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:LFC_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:LFC_SC_PD_DC_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:LFC_SC_PD_DC_CND_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:LFC_SC_PD_DC_lowpass_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:LFC_SC_PD_RF_11MHz_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:LFC_SC_PD_RF_11MHz_I_CAL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:LFC_SC_PD_RF_11MHz_I_FIL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:LFC_SC_PD_RF_11MHz_I_NONFIL_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:LFC_SC_PD_RF_11MHz_I_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:LFC_Z_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:LFC_Z_CORR_ENB_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:LFC_Z_GR_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:LFC_Z_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:LFC_Z_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:LFC_Z_PRE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:LFC_Z_SC_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:LNFS_Demod_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:LNFS_Demod_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:LNFS_RAMS_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:LNFS_RAMS_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:LSC_ALS_ARMS_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:LSC_ALS_CARM_REFL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:LSC_ALS_DARM_REFL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:LSC_ALS_NArm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:LSC_ALS_NArm_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:LSC_ALS_NArm_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:LSC_ALS_NArm_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:LSC_ALS_NArm_RAW_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:LSC_ALS_NArm_REL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:LSC_ALS_NArm_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:LSC_ALS_WArm_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:LSC_ALS_WArm_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:LSC_ALS_WArm_ERR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:LSC_ALS_WArm_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:LSC_ALS_WArm_RAW_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:LSC_ALS_WArm_REL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:LSC_ALS_WArm_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:LSC_ARMS_LOCK_ON_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:LSC_Acl_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:LSC_Acl_Moni_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:LSC_Acl_Moni_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:LSC_Acl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:LSC_B1p_DC_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:LSC_B1p_DC_TRIG_p_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:LSC_B1p_MICH_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:LSC_B1p_SUM_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:LSC_B2_112MHz_MAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:LSC_B2_112MHz_MAG_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:LSC_B2_112MHz_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:LSC_B2_12MHz_MAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:LSC_B2_12MHz_MAG_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:LSC_B2_12MHz_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:LSC_B2_6MHz_I_COMP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:LSC_B2_DC_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:LSC_B4_112MHz_LP_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:LSC_B4_112MHz_MAG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:LSC_B4_112MHz_MAG_GRAD_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:LSC_B4_112MHz_MAG_GRAD_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:LSC_B4_112MHz_MAG_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:LSC_B4_112MHz_MAG_TRIG_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr