OUTPUT DIRECTORY ./report OUTPUT VERBOSITY 1 TARGET OMICRON V1:Hrec_hoft_16384Hz TARGET CLUSTERDT 0.1 TARGET SNRMIN 7 COINC TIMEWIN 1.0 VETO UPMIN 0.4 VETO UMIN 10 VETO PRINT 0 VETO PERF 5 8 10 20 VETO PERFPRINT 1 0 SOURCE CLUSTERDT 0.1 SOURCE OMICRON V1:FCEM_LC_PSD2_1Y_raw SOURCE OMICRON V1:FCEM_LC_PSD2_20X_raw SOURCE OMICRON V1:FCEM_LC_PSD2_20Y_raw SOURCE OMICRON V1:FCEM_LC_PSD2_SUM_raw SOURCE OMICRON V1:FCEM_LC_PSD3_1X_raw SOURCE OMICRON V1:FCEM_LC_PSD3_1Y_raw SOURCE OMICRON V1:FCEM_LC_PSD3_20X_raw SOURCE OMICRON V1:FCEM_LC_PSD3_20Y_raw SOURCE OMICRON V1:FCEM_LC_PSD3_SUM_raw SOURCE OMICRON V1:FCEM_LC_PSD4_1X_raw SOURCE OMICRON V1:FCEM_LC_PSD4_1Y_CAL SOURCE OMICRON V1:FCEM_LC_PSD4_1Y_raw SOURCE OMICRON V1:FCEM_LC_PSD4_20X_raw SOURCE OMICRON V1:FCEM_LC_PSD4_20Y_raw SOURCE OMICRON V1:FCEM_LC_PSD4_SUM_raw SOURCE OMICRON V1:FCEM_LC_TX_line SOURCE OMICRON V1:FCEM_LC_TY_line SOURCE OMICRON V1:FCEM_LC_TZ_line SOURCE OMICRON V1:FCEM_LC_elapsed_time SOURCE OMICRON V1:FCEM_LC_loop_act SOURCE OMICRON V1:FCEM_SBE_CfgChange SOURCE OMICRON V1:FCEM_SBE_elapsed_time SOURCE OMICRON V1:FCIM_LC_ACT_MARH_B_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARH_F_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARH_L_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARH_R_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARV_B_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARV_F_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARV_L_raw SOURCE OMICRON V1:FCIM_LC_ACT_MARV_R_raw SOURCE OMICRON V1:FCIM_LC_ACT_MIR_B_raw SOURCE OMICRON V1:FCIM_LC_ACT_MIR_L_raw SOURCE OMICRON V1:FCIM_LC_ACT_MIR_R_raw SOURCE OMICRON V1:FCIM_LC_ACT_MIR_T_raw SOURCE OMICRON V1:FCIM_LC_CC_COARSE_ENBL SOURCE OMICRON V1:FCIM_LC_CfgChange SOURCE OMICRON V1:FCIM_LC_HD_CC_COARSE_OUT SOURCE OMICRON V1:FCIM_LC_MAR_H_B SOURCE OMICRON V1:FCIM_LC_MAR_H_F SOURCE OMICRON V1:FCIM_LC_MAR_H_L SOURCE OMICRON V1:FCIM_LC_MAR_H_R SOURCE OMICRON V1:FCIM_LC_MAR_TX SOURCE OMICRON V1:FCIM_LC_MAR_TX_ACT SOURCE OMICRON V1:FCIM_LC_MAR_TX_CORR SOURCE OMICRON V1:FCIM_LC_MAR_TX_CORR_ENB SOURCE OMICRON V1:FCIM_LC_MAR_TX_ERR SOURCE OMICRON V1:FCIM_LC_MAR_TX_THRE SOURCE OMICRON V1:FCIM_LC_MAR_TY SOURCE OMICRON V1:FCIM_LC_MAR_TY_2 SOURCE OMICRON V1:FCIM_LC_MAR_TY_ACT SOURCE OMICRON V1:FCIM_LC_MAR_TY_CORR SOURCE OMICRON V1:FCIM_LC_MAR_TY_CORR_ENB SOURCE OMICRON V1:FCIM_LC_MAR_TY_ERR SOURCE OMICRON V1:FCIM_LC_MAR_TY_THRE SOURCE OMICRON V1:FCIM_LC_MAR_TZ SOURCE OMICRON V1:FCIM_LC_MAR_TZ_ACT SOURCE OMICRON V1:FCIM_LC_MAR_TZ_CORR SOURCE OMICRON V1:FCIM_LC_MAR_TZ_CORR_ENB SOURCE OMICRON V1:FCIM_LC_MAR_TZ_ERR SOURCE OMICRON V1:FCIM_LC_MAR_TZ_THRE SOURCE OMICRON V1:FCIM_LC_MAR_V_B SOURCE OMICRON V1:FCIM_LC_MAR_V_F SOURCE OMICRON V1:FCIM_LC_MAR_V_L SOURCE OMICRON V1:FCIM_LC_MAR_V_R SOURCE OMICRON V1:FCIM_LC_MIR_B SOURCE OMICRON V1:FCIM_LC_MIR_L SOURCE OMICRON V1:FCIM_LC_MIR_R SOURCE OMICRON V1:FCIM_LC_MIR_T SOURCE OMICRON V1:FCIM_LC_MIR_TX SOURCE OMICRON V1:FCIM_LC_MIR_TX_ACT SOURCE OMICRON V1:FCIM_LC_MIR_TX_ERR SOURCE OMICRON V1:FCIM_LC_MIR_TY SOURCE OMICRON V1:FCIM_LC_MIR_TY_ACT SOURCE OMICRON V1:FCIM_LC_MIR_TY_ERR SOURCE OMICRON V1:FCIM_LC_MIR_Z SOURCE OMICRON V1:FCIM_LC_MIR_Z_ACT SOURCE OMICRON V1:FCIM_LC_MIR_Z_ERR SOURCE OMICRON V1:FCIM_LC_NOISE SOURCE OMICRON V1:FCIM_LC_PSD1_1X SOURCE OMICRON V1:FCIM_LC_PSD1_1X_NORM SOURCE OMICRON V1:FCIM_LC_PSD1_1X_raw SOURCE OMICRON V1:FCIM_LC_PSD1_1Y_raw SOURCE OMICRON V1:FCIM_LC_PSD1_20X_raw SOURCE OMICRON V1:FCIM_LC_PSD1_20Y_raw SOURCE OMICRON V1:FCIM_LC_PSD1_SUM_raw SOURCE OMICRON V1:FCIM_LC_PSD2_1X_raw SOURCE OMICRON V1:FCIM_LC_PSD2_1Y_raw SOURCE OMICRON V1:FCIM_LC_PSD2_20X_raw SOURCE OMICRON V1:FCIM_LC_PSD2_20Y_raw SOURCE OMICRON V1:FCIM_LC_PSD2_SUM_raw SOURCE OMICRON V1:FCIM_LC_PSD3_1X_raw SOURCE OMICRON V1:FCIM_LC_PSD3_1Y_raw SOURCE OMICRON V1:FCIM_LC_PSD3_20X_raw SOURCE OMICRON V1:FCIM_LC_PSD3_20Y_raw SOURCE OMICRON V1:FCIM_LC_PSD3_SUM_raw SOURCE OMICRON V1:FCIM_LC_PSD4_1X_raw SOURCE OMICRON V1:FCIM_LC_PSD4_1Y_raw SOURCE OMICRON V1:FCIM_LC_PSD4_20X_raw SOURCE OMICRON V1:FCIM_LC_PSD4_20Y_raw SOURCE OMICRON V1:FCIM_LC_PSD4_SUM_raw