OUTPUT DIRECTORY ./report OUTPUT VERBOSITY 1 TARGET OMICRON V1:Hrec_hoft_16384Hz TARGET CLUSTERDT 0.1 TARGET SNRMIN 7 COINC TIMEWIN 1.0 VETO UPMIN 0.4 VETO UMIN 10 VETO PRINT 0 VETO PERF 5 8 10 20 VETO PERFPRINT 1 0 SOURCE CLUSTERDT 0.1 SOURCE OMICRON V1:EQB2_IR_QD4_DC4 SOURCE OMICRON V1:EQB2_IR_QD4_GALVO_X_CORR SOURCE OMICRON V1:EQB2_IR_QD4_GALVO_X_CORR_notsafe SOURCE OMICRON V1:EQB2_IR_QD4_GALVO_Y_CORR SOURCE OMICRON V1:EQB2_IR_QD4_GALVO_Y_CORR_notsafe SOURCE OMICRON V1:EQB2_IR_QD4_GALVO_status SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_MM_I SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_MM_Q SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_X_I SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_X_NORM SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_X_Q SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_Y_I SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_Y_NORM SOURCE OMICRON V1:EQB2_IR_QD4_RF_11MHz_Y_Q SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_MM_I SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_MM_Q SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_X_I SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_X_NORM SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_X_Q SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_Y_I SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_Y_NORM SOURCE OMICRON V1:EQB2_IR_QD4_RF_4MHz_Y_Q SOURCE OMICRON V1:EQB2_IR_QD4_SUM SOURCE OMICRON V1:EQB2_IR_QD4_X SOURCE OMICRON V1:EQB2_IR_QD4_X_NORM SOURCE OMICRON V1:EQB2_IR_QD4_Y SOURCE OMICRON V1:EQB2_IR_QD4_Y_NORM SOURCE OMICRON V1:EQB2_QD_CfgChange SOURCE OMICRON V1:EQB2_QD_elapsed_time SOURCE OMICRON V1:EQB2_SC_PD_RF_11MHz_I SOURCE OMICRON V1:EQB2_SC_PD_RF_11MHz_Q SOURCE OMICRON V1:EnvDemod_CfgChange SOURCE OMICRON V1:EnvDemod_elapsed_time SOURCE OMICRON V1:FCEB_GR_FF_PSD_20X SOURCE OMICRON V1:FCEB_GR_FF_PSD_20Y SOURCE OMICRON V1:FCEB_GR_FF_PSD_SUM SOURCE OMICRON V1:FCEB_GR_FF_PSD_X SOURCE OMICRON V1:FCEB_GR_FF_PSD_Y SOURCE OMICRON V1:FCEB_GR_NF_PSD_SUM SOURCE OMICRON V1:FCEB_GR_NF_PSD_X SOURCE OMICRON V1:FCEB_GR_NF_PSD_Y SOURCE OMICRON V1:FCEB_GR_PD_DC SOURCE OMICRON V1:FCEB_GR_PD_demod SOURCE OMICRON V1:FCEB_IR_PD_DC SOURCE OMICRON V1:FCEM_LC_ACT_MARH_B_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARH_F_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARH_L_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARH_R_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARV_B_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARV_F_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARV_L_raw SOURCE OMICRON V1:FCEM_LC_ACT_MARV_R_raw SOURCE OMICRON V1:FCEM_LC_ACT_MIR_B_raw SOURCE OMICRON V1:FCEM_LC_ACT_MIR_L_raw SOURCE OMICRON V1:FCEM_LC_ACT_MIR_R_raw SOURCE OMICRON V1:FCEM_LC_ACT_MIR_T_raw SOURCE OMICRON V1:FCEM_LC_CfgChange SOURCE OMICRON V1:FCEM_LC_MAR_H_B SOURCE OMICRON V1:FCEM_LC_MAR_H_F SOURCE OMICRON V1:FCEM_LC_MAR_H_L SOURCE OMICRON V1:FCEM_LC_MAR_H_R SOURCE OMICRON V1:FCEM_LC_MAR_TX SOURCE OMICRON V1:FCEM_LC_MAR_TX_ACT SOURCE OMICRON V1:FCEM_LC_MAR_TX_CORR SOURCE OMICRON V1:FCEM_LC_MAR_TX_CORR_ENB SOURCE OMICRON V1:FCEM_LC_MAR_TX_ERR SOURCE OMICRON V1:FCEM_LC_MAR_TY SOURCE OMICRON V1:FCEM_LC_MAR_TY_2 SOURCE OMICRON V1:FCEM_LC_MAR_TY_ACT SOURCE OMICRON V1:FCEM_LC_MAR_TY_CORR SOURCE OMICRON V1:FCEM_LC_MAR_TY_CORR_ENB SOURCE OMICRON V1:FCEM_LC_MAR_TY_ERR SOURCE OMICRON V1:FCEM_LC_MAR_TZ SOURCE OMICRON V1:FCEM_LC_MAR_TZ_ACT SOURCE OMICRON V1:FCEM_LC_MAR_TZ_CORR SOURCE OMICRON V1:FCEM_LC_MAR_TZ_CORR_ENB SOURCE OMICRON V1:FCEM_LC_MAR_TZ_ERR SOURCE OMICRON V1:FCEM_LC_MAR_V_B SOURCE OMICRON V1:FCEM_LC_MAR_V_F SOURCE OMICRON V1:FCEM_LC_MAR_V_L SOURCE OMICRON V1:FCEM_LC_MAR_V_R SOURCE OMICRON V1:FCEM_LC_MIR_TX SOURCE OMICRON V1:FCEM_LC_MIR_TX_ACT SOURCE OMICRON V1:FCEM_LC_MIR_TX_ERR SOURCE OMICRON V1:FCEM_LC_MIR_TY SOURCE OMICRON V1:FCEM_LC_MIR_TY_ACT SOURCE OMICRON V1:FCEM_LC_MIR_TY_ERR SOURCE OMICRON V1:FCEM_LC_MIR_Z SOURCE OMICRON V1:FCEM_LC_MIR_Z_ACT SOURCE OMICRON V1:FCEM_LC_MIR_Z_CORR SOURCE OMICRON V1:FCEM_LC_MIR_Z_ERR SOURCE OMICRON V1:FCEM_LC_NOISE SOURCE OMICRON V1:FCEM_LC_PSD1_1X SOURCE OMICRON V1:FCEM_LC_PSD1_1X_NORM SOURCE OMICRON V1:FCEM_LC_PSD1_1X_raw SOURCE OMICRON V1:FCEM_LC_PSD1_1Y_raw SOURCE OMICRON V1:FCEM_LC_PSD1_20X_raw SOURCE OMICRON V1:FCEM_LC_PSD1_20Y_raw SOURCE OMICRON V1:FCEM_LC_PSD1_SUM_raw SOURCE OMICRON V1:FCEM_LC_PSD2_1X_raw