VetoPerf analysis over V1:Hrec_hoft_16384Hz


Summary

VetoPerf version:3.2.0: documentation gitlab repository
VetoPerf run by:unknown
VetoPerf processing time:4 h, 36 min, 37 s
Processing Date:Fri Jan 19 16:39:46 2024 (UTC)
Requested start:1387467885 → Sun Dec 24 15:44:27 2023 (UTC)
Requested stop:1388080814 → Sun Dec 31 17:59:56 2023 (UTC)
Requested livetime:452627 sec → 5.239 days
Requested segments:vp.insegments.txt
Summary text file:vp.summary.txt

Triggers (V1:Hrec_hoft_16384Hz - OMICRON)

Number of raw triggers:4316241
Number of raw clusters:71452
Number of active clusters:71452 (SNR > 5.000) 592 (SNR > 8.000) 470 (SNR > 10.000) 402 (SNR > 20.000)

Vetoes

Number of vetoes:100
Dead time: Integrated time when the veto is active. We note d the fraction of the total livetime (452627 s) when the veto is active.
Efficiency (ε):This is the fraction of V1:Hrec_hoft_16384Hz triggers which are vetoed.
ε/d:This factor is larger than 1 when the veto rejects more triggers than a random veto.
V1:Hrec_hoft_16384Hz: 71452 clusters

V0: V1:AFC_Ctrl_CfgChange_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V1: V1:AFC_Ctrl_elapsed_time_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V2: V1:AFC_DRIFT_CTRL_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V3: V1:AFC_DRIFT_CTRL_ENBL_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V4: V1:AFC_FCEM_DRIFT_TX_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V5: V1:AFC_FCEM_DRIFT_TX_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V6: V1:AFC_FCEM_DRIFT_TX_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V7: V1:AFC_FCEM_DRIFT_TX_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V8: V1:AFC_FCEM_DRIFT_TX_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V9: V1:AFC_FCEM_DRIFT_TY_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V10: V1:AFC_FCEM_DRIFT_TY_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V11: V1:AFC_FCEM_DRIFT_TY_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V12: V1:AFC_FCEM_DRIFT_TY_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V13: V1:AFC_FCEM_DRIFT_TY_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V14: V1:AFC_FCEM_SC_TX_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V15: V1:AFC_FCEM_SC_TX_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V16: V1:AFC_FCEM_SC_TY_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V17: V1:AFC_FCEM_SC_TY_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V18: V1:AFC_FCIM_DRIFT_TX_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V19: V1:AFC_FCIM_DRIFT_TX_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V20: V1:AFC_FCIM_DRIFT_TX_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V21: V1:AFC_FCIM_DRIFT_TX_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V22: V1:AFC_FCIM_DRIFT_TX_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V23: V1:AFC_FCIM_DRIFT_TY_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V24: V1:AFC_FCIM_DRIFT_TY_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V25: V1:AFC_FCIM_DRIFT_TY_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V26: V1:AFC_FCIM_DRIFT_TY_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V27: V1:AFC_FCIM_DRIFT_TY_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V28: V1:AFC_FCIM_SC_TX_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V29: V1:AFC_FCIM_SC_TX_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V30: V1:AFC_FCIM_SC_TY_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V31: V1:AFC_FCIM_SC_TY_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V32: V1:AFC_FF_PSD_X_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V33: V1:AFC_FF_PSD_Y_NORM_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V34: V1:AFC_FLT_CORR_FCEM_TX_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V35: V1:AFC_FLT_CORR_FCEM_TY_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V36: V1:AFC_FLT_CORR_FCIM_TX_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V37: V1:AFC_FLT_CORR_FCIM_TY_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V38: V1:AFC_GREEN_AA_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V39: V1:AFC_GREEN_AA_ENBL_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V40: V1:AFC_GR_AA_NOISE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V41: V1:AFC_GR_BPC2_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V42: V1:AFC_GR_BPC2_ENBL_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V43: V1:AFC_GR_BPC_CTRL_ENBL_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V44: V1:AFC_GR_BPC_CTRL_ENBL_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V45: V1:AFC_GR_FCEM_AA_TX_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V46: V1:AFC_GR_FCEM_AA_TX_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V47: V1:AFC_GR_FCEM_AA_TX_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V48: V1:AFC_GR_FCEM_AA_TX_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V49: V1:AFC_GR_FCEM_AA_TX_PRE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V50: V1:AFC_GR_FCEM_AA_TX_SET_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V51: V1:AFC_GR_FCEM_AA_TY_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V52: V1:AFC_GR_FCEM_AA_TY_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V53: V1:AFC_GR_FCEM_AA_TY_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V54: V1:AFC_GR_FCEM_AA_TY_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V55: V1:AFC_GR_FCEM_AA_TY_PRE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V56: V1:AFC_GR_FCEM_AA_TY_SET_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V57: V1:AFC_GR_FCIM_AA_TX_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V58: V1:AFC_GR_FCIM_AA_TX_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V59: V1:AFC_GR_FCIM_AA_TX_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V60: V1:AFC_GR_FCIM_AA_TX_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V61: V1:AFC_GR_FCIM_AA_TX_PRE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V62: V1:AFC_GR_FCIM_AA_TX_SET_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V63: V1:AFC_GR_FCIM_AA_TY_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V64: V1:AFC_GR_FCIM_AA_TY_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V65: V1:AFC_GR_FCIM_AA_TY_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V66: V1:AFC_GR_FCIM_AA_TY_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V67: V1:AFC_GR_FCIM_AA_TY_PRE_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V68: V1:AFC_GR_FCIM_AA_TY_SET_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V69: V1:AFC_GR_M5_BPC2_X_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V70: V1:AFC_GR_M5_BPC2_X_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V71: V1:AFC_GR_M5_BPC2_X_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V72: V1:AFC_GR_M5_BPC2_X_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V73: V1:AFC_GR_M5_BPC2_Y_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V74: V1:AFC_GR_M5_BPC2_Y_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V75: V1:AFC_GR_M5_BPC2_Y_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V76: V1:AFC_GR_M5_BPC2_Y_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V77: V1:AFC_GR_M5_BPC_X_CMD_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V78: V1:AFC_GR_M5_BPC_X_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V79: V1:AFC_GR_M5_BPC_X_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V80: V1:AFC_GR_M5_BPC_X_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V81: V1:AFC_GR_M5_BPC_X_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V82: V1:AFC_GR_M5_BPC_X_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V83: V1:AFC_GR_M5_BPC_Y_CMD_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V84: V1:AFC_GR_M5_BPC_Y_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V85: V1:AFC_GR_M5_BPC_Y_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V86: V1:AFC_GR_M5_BPC_Y_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V87: V1:AFC_GR_M5_BPC_Y_demod_I_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V88: V1:AFC_GR_M5_BPC_Y_demod_Q_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V89: V1:AFC_GR_M7_BPC2_X_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V90: V1:AFC_GR_M7_BPC2_X_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V91: V1:AFC_GR_M7_BPC2_X_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V92: V1:AFC_GR_M7_BPC2_X_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V93: V1:AFC_GR_M7_BPC2_Y_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V94: V1:AFC_GR_M7_BPC2_Y_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V95: V1:AFC_GR_M7_BPC2_Y_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V96: V1:AFC_GR_M7_BPC2_Y_POST_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V97: V1:AFC_GR_M7_BPC_X_CMD_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V98: V1:AFC_GR_M7_BPC_X_CORR_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


V99: V1:AFC_GR_M7_BPC_X_INPUT_0 (ε = 0.000%, ε/d = 0.000) [click here to expand/hide] [link to here]


Florent Robinet, florent.robinet@ijclab.in2p3.fr